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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode AAA</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b> <a href="S17_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_02.HTM">17.2 Instruction Format</a><br>
<b>next:</b><a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM"> AAD ASCII Adjust AX before Division</a>
<p>
<hr>
<p>
<h1>AAA -- ASCII Adjust after Addition</h1>
<pre>
Opcode Instruction Clocks Description
37 AAA 4 ASCII adjust AL after addition
</pre>
<h2>Operation</h2>
<pre>
IF ((AL AND 0FH) &gt; 9) OR (AF = 1)
THEN
AL := (AL + 6) AND 0FH;
AH := AH + 1;
AF := 1;
CF := 1;
ELSE
CF := 0;
AF := 0;
FI;
</pre>
<h2>Description</h2>
Execute AAA only following an <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> instruction that leaves a byte result in the AL register. The lower nibbles of the operands of the <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> instruction should be in the range 0 through 9 (BCD digits). In this case, AAA adjusts AL to contain the correct decimal digit result. If the addition produced a decimal carry, the AH register is incremented, and the carry and auxiliary carry flags are set to 1. If there was no decimal carry, the carry and auxiliary flags are set to 0 and AH is unchanged. In either case, AL is left with its top nibble set to 0. To convert AL to an ASCII result, follow the AAA instruction with <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a> AL, 30H.
<h2>Flags Affected</h2>
AF and CF as described above; OF, SF, ZF, and PF are undefined
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b> <a href="S17_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_02.HTM">17.2 Instruction Format</a><br>
<b>next:</b><a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM"> AAD ASCII Adjust AX before Division</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode AAD</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAA.HTM"> AAA ASCII Adjust after Addition</a><br>
<b>next:</b><a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM"> AAM ASCII Adjust AX after Multiply</a>
<p>
<hr>
<p>
<h1>AAD -- ASCII Adjust AX before Division</h1>
<pre>
Opcode Instruction Clocks Description
D5 0A AAD 19 ASCII adjust AX before division
</pre>
<h2>Operation</h2>
<pre>
AL := AH * 10 + AL;
AH := 0;
</pre>
<h2>Description</h2>
AAD is used to prepare two unpacked BCD digits (the least-significant digit in AL, the most-significant digit in AH) for a division operation that will yield an unpacked result. This is accomplished by setting AL to AL + (10 * AH), and then setting AH to 0. AX is then equal to the binary equivalent of the original unpacked two-digit number.
<h2>Flags Affected</h2>
SF, ZF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>; OF, AF, and CF are undefined
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAA.HTM"> AAA ASCII Adjust after Addition</a><br>
<b>next:</b><a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM"> AAM ASCII Adjust AX after Multiply</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode AAM</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM"> AAD ASCII Adjust AX before Division</a><br>
<b>next:</b><a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM"> AAS ASCII Adjust AL after Subtraction</a>
<p>
<hr>
<p>
<h1>AAM -- ASCII Adjust AX after Multiply</h1>
<pre>
Opcode Instruction Clocks Description
D4 0A AAM 17 ASCII adjust AX after multiply
</pre>
<h2>Operation</h2>
<pre>
AH := AL / 10;
AL := AL MOD 10;
</pre>
<h2>Description</h2>
Execute AAM only after executing a <a href="MUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MUL.HTM">MUL</a> instruction between two unpacked BCD digits that leaves the result in the AX register. Because the result is less than 100, it is contained entirely in the AL register. AAM unpacks the AL result by dividing AL by 10, leaving the quotient (most-significant digit) in AH and the remainder (least-significant digit) in AL.
<h2>Flags Affected</h2>
SF, ZF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>; OF, AF, and CF are undefined
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM"> AAD ASCII Adjust AX before Division</a><br>
<b>next:</b><a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM"> AAS ASCII Adjust AL after Subtraction</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode AAS</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM"> AAM ASCII Adjust AX after Multiply</a><br>
<b>next:</b><a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM"> ADC Add with Carry</a>
<p>
<hr>
<p>
<h1>AAS -- ASCII Adjust AL after Subtraction</h1>
<pre>
Opcode Instruction Clocks Description
3F AAS 4 ASCII adjust AL after subtraction
</pre>
<h2>Operation</h2>
<pre>
IF (AL AND 0FH) &gt; 9 OR AF = 1
THEN
AL := AL - 6;
AL := AL AND 0FH;
AH := AH - 1;
AF := 1;
CF := 1;
ELSE
CF := 0;
AF := 0;
FI;
</pre>
<h2>Description</h2>
Execute AAS only after a <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> instruction that leaves the byte result in the AL register. The lower nibbles of the operands of the <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> instruction must have been in the range 0 through 9 (BCD digits). In this case, AAS adjusts AL so it contains the correct decimal digit result. If the subtraction produced a decimal carry, the AH register is decremented, and the carry and auxiliary carry flags are set to 1. If no decimal carry occurred, the carry and auxiliary carry flags are set to 0, and AH is unchanged. In either case, AL is left with its top nibble set to 0. To convert AL to an ASCII result, follow the AAS with <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a> AL, 30H.
<h2>Flags Affected</h2>
AF and CF as described above; OF, SF, ZF, and PF are undefined
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM"> AAM ASCII Adjust AX after Multiply</a><br>
<b>next:</b><a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM"> ADC Add with Carry</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode ADC</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM"> AAS ASCII Adjust AL after Subtraction</a><br>
<b>next:</b><a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM"> ADD Add</a>
<p>
<hr>
<p>
<h1>ADC -- Add with Carry</h1>
<pre>
Opcode Instruction Clocks Description
14 ib ADC AL,imm8 2 Add with carry immediate byte to AL
15 iw ADC AX,imm16 2 Add with carry immediate word to AX
15 id ADC EAX,imm32 2 Add with carry immediate dword to EAX
80 /2 ib ADC r/m8,imm8 2/7 Add with carry immediate byte to r/m
byte
81 /2 iw ADC r/m16,imm16 2/7 Add with carry immediate word to r/m
word
81 /2 id ADC r/m32,imm32 2/7 Add with CF immediate dword to r/m
dword
83 /2 ib ADC r/m16,imm8 2/7 Add with CF sign-extended immediate
byte to r/m word
83 /2 ib ADC r/m32,imm8 2/7 Add with CF sign-extended immediate
byte into r/m dword
10 /r ADC r/m8,r8 2/7 Add with carry byte register to r/m
byte
11 /r ADC r/m16,r16 2/7 Add with carry word register to r/m
word
11 /r ADC r/m32,r32 2/7 Add with CF dword register to r/m dword
12 /r ADC r8,r/m8 2/6 Add with carry r/m byte to byte
register
13 /r ADC r16,r/m16 2/6 Add with carry r/m word to word
register
13 /r ADC r32,r/m32 2/6 Add with CF r/m dword to dword register
</pre>
<h2>Operation</h2>
<pre>
DEST := DEST + SRC + CF;
</pre>
<h2>Description</h2>
ADC performs an integer addition of the two operands DEST and SRC and the carry flag, CF. The result of the addition is assigned to the first operand (DEST), and the flags are set accordingly. ADC is usually executed as part of a multi-byte or multi-word addition operation. When an immediate byte value is added to a word or doubleword operand, the immediate value is first sign-extended to the size of the word or doubleword operand.
<h2>Flags Affected</h2>
OF, SF, ZF, AF, CF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) if page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM"> AAS ASCII Adjust AL after Subtraction</a><br>
<b>next:</b><a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM"> ADD Add</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode ADD</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM"> ADC Add with Carry</a><br>
<b>next:</b><a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM"> AND Logical AND</a>
<p>
<hr>
<p>
<h1>ADD -- Add</h1>
<pre>
Opcode Instruction Clocks Description
04 ib ADD AL,imm8 2 Add immediate byte to AL
05 iw ADD AX,imm16 2 Add immediate word to AX
05 id ADD EAX,imm32 2 Add immediate dword to EAX
80 /0 ib ADD r/m8,imm8 2/7 Add immediate byte to r/m byte
81 /0 iw ADD r/m16,imm16 2/7 Add immediate word to r/m word
81 /0 id ADD r/m32,imm32 2/7 Add immediate dword to r/m dword
83 /0 ib ADD r/m16,imm8 2/7 Add sign-extended immediate byte
to r/m word
83 /0 ib ADD r/m32,imm8 2/7 Add sign-extended immediate byte
to r/m dword
00 /r ADD r/m8,r8 2/7 Add byte register to r/m byte
01 /r ADD r/m16,r16 2/7 Add word register to r/m word
01 /r ADD r/m32,r32 2/7 Add dword register to r/m dword
02 /r ADD r8,r/m8 2/6 Add r/m byte to byte register
03 /r ADD r16,r/m16 2/6 Add r/m word to word register
03 /r ADD r32,r/m32 2/6 Add r/m dword to dword register
</pre>
<h2>Operation</h2>
<pre>
DEST := DEST + SRC;
</pre>
<h2>Description</h2>
ADD performs an integer addition of the two operands (DEST and SRC). The result of the addition is assigned to the first operand (DEST), and the flags are set accordingly.
<p>When an immediate byte is added to a word or doubleword operand, the immediate value is sign-extended to the size of the word or doubleword operand.
<h2>Flags Affected</h2>
OF, SF, ZF, AF, CF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM"> ADC Add with Carry</a><br>
<b>next:</b><a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM"> AND Logical AND</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode AND</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM"> ADD Add</a><br>
<b>next:</b><a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM"> ARPL Adjust RPL Field of Selector</a>
<p>
<hr>
<p>
<h1>AND -- Logical AND</h1>
<pre>
Opcode Instruction Clocks Description
24 ib AND AL,imm8 2 AND immediate byte to AL
25 iw AND AX,imm16 2 AND immediate word to AX
25 id AND EAX,imm32 2 AND immediate dword to EAX
80 /4 ib AND r/m8,imm8 2/7 AND immediate byte to r/m byte
81 /4 iw AND r/m16,imm16 2/7 AND immediate word to r/m word
81 /4 id AND r/m32,imm32 2/7 AND immediate dword to r/m dword
83 /4 ib AND r/m16,imm8 2/7 AND sign-extended immediate byte
with r/m word
83 /4 ib AND r/m32,imm8 2/7 AND sign-extended immediate byte
with r/m dword
20 /r AND r/m8,r8 2/7 AND byte register to r/m byte
21 /r AND r/m16,r16 2/7 AND word register to r/m word
21 /r AND r/m32,r32 2/7 AND dword register to r/m dword
22 /r AND r8,r/m8 2/6 AND r/m byte to byte register
23 /r AND r16,r/m16 2/6 AND r/m word to word register
23 /r AND r32,r/m32 2/6 AND r/m dword to dword register
</pre>
<h2>Operation</h2>
<pre>
DEST := DEST AND SRC;
CF := 0;
OF := 0;
</pre>
<h2>Description</h2>
Each bit of the result of the AND instruction is a 1 if both corresponding bits of the operands are 1; otherwise, it becomes a 0.
<h2>Flags Affected</h2>
CF := 0, OF := 0; PF, SF, and ZF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM"> ADD Add</a><br>
<b>next:</b><a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM"> ARPL Adjust RPL Field of Selector</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- APPENDICES</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a>
<p>
<hr>
<p>
<h1>APPENDICES</h1>
<a href="APPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPA.HTM">Appendix A -- Opcode Map</a><br>
<a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
<a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
<a href="APPD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPD.HTM">Appendix D -- Condition Codes</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a>
</body>

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<title>80386 Programmer's Reference Manual -- Appendix A</title>
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<b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>next:</b> <a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
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<hr>
<p>
<h1>Appendix A -- Opcode Map</h1>
The opcode tables that follow aid in interpreting 80386 object code. Use the high-order four bits of the opcode as an index to a row of the opcode table; use the low-order four bits as an index to a column of the table. If the opcode is 0FH, refer to the two-byte opcode table and use the second byte of the opcode to index the rows and columns of that table.
<h3>Key to Abbreviations</h3>
Operands are identified by a two-character code of the form Zz. The first character, an uppercase letter, specifies the addressing method; the second character, a lowercase letter, specifies the type of operand.
<h3>Codes for Addressing Method</h3>
<dl>
<dt>A
<dd>Direct address; the instruction has no modR/M byte; the address of the operand is encoded in the instruction; no base register, index register, or scaling factor can be applied; e.g., far <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> (EA).
<dt>C
<dd>The reg field of the modR/M byte selects a control register; e.g., <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> (0F20, 0F22).
<dt>D
<dd>The reg field of the modR/M byte selects a debug register; e.g., <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> (0F21,0F23).
<dt>E
<dd>A modR/M byte follows the opcode and specifies the operand. The operand is either a general register or a memory address. If it is a memory address, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, a displacement.
<dt>F
<dd>Flags Register.
<dt>G
<dd>The reg field of the modR/M byte selects a general register; e.g., <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> (00).
<dt>I
<dd>Immediate data. The value of the operand is encoded in subsequent bytes of the instruction.
<dt>J
<dd>The instruction contains a relative offset to be added to the instruction pointer register; e.g., <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> short, <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a>.
<dt>M
<dd>The modR/M byte may refer only to memory; e.g., <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LES</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a>.
<dt>O
<dd>The instruction has no modR/M byte; the offset of the operand is coded as a word or double word (depending on address size attribute) in the instruction. No base register, index register, or scaling factor can be applied; e.g., <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> (A0-A3).
<dt>R
<dd>The mod field of the modR/M byte may refer only to a general register; e.g., <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> (0F20-0F24, 0F26).
<dt>S
<dd>The reg field of the modR/M byte selects a segment register; e.g., <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> (8C,8E).
<dt>T
<dd>The reg field of the modR/M byte selects a test register; e.g., <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> (0F24,0F26).
<dt>X
<dd>Memory addressed by DS:SI; e.g., <a href="MOVS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVS.HTM">MOVS</a>, <a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM">CMPS</a>, <a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTS</a>, <a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM">LODS</a>, <a href="SCAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SCAS.HTM">SCAS</a>.
<dt>Y
<dd>Memory addressed by ES:DI; e.g., <a href="MOVS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVS.HTM">MOVS</a>, <a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM">CMPS</a>, <a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INS</a>, <a href="STOS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STOS.HTM">STOS</a>.
</dl>
<h3>Codes for Operant Type</h3>
<dl>
<dt>a
<dd>Two one-word operands in memory or two double-word operands in memory, depending on operand size attribute (used only by <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a>)
<dt>b
<dd>Byte (regardless of operand size attribute)
<dt>c
<dd>Byte or word, depending on operand size attribute.
<dt>d
<dd>Double word (regardless of operand size attribute)
<dt>p
<dd>32-bit or 48-bit pointer, depending on operand size attribute.
<dt>s
<dd>Six-byte pseudo-descriptor
<dt>v
<dd>Word or double word, depending on operand size attribute.
<dt>w
<dd>Word (regardless of operand size attribute)
</dl>
<h3>Register Codes</h3>
When an operand is a specific register encoded in the opcode, the register is identified by its name; e.g., AX, CL, or ESI. The name of the register indicates whether the register is 32-, 16-, or 8-bits wide. A register identifier of the form eXX is used when the width of the register depends on the operand size attribute; for example, eAX indicates that the AX register is used when the operand size attribute is 16 and the EAX register is used when the operand size attribute is 32.
<h3>One-Byte Opcode Map</h3>
<pre>
0 1 2 3 4 5 6 7 8 9 A B C D E F
+-----------------------------------------------------------+--------+--------+-----------------------------------------------------------+--------+--------+
| <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> | <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | 2-byte |
0|---------+---------+---------+---------+---------+---------+ | +---------+---------+---------+---------+---------+---------+ | |
| Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | ES | ES | Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | CS | escape |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM">ADC</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> | <a href="SBB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SBB.HTM">SBB</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> |
1|---------+---------+---------+---------+---------+---------+ | +---------+---------+---------+---------+---------+---------+ | |
| Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | SS | SS | Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | DS | DS |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND</a> | SEG | | <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> | SEG | |
2|---------+---------+---------+---------+---------+---------+ | <a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM">DAA</a> +---------+---------+---------+---------+---------+---------+ | <a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM">DAS</a> |
| Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | =ES | | Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | =CS | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="XOR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XOR.HTM">XOR</a> | SEG | | <a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM">CMP</a> | SEG | |
3|---------+---------+---------+---------+---------+---------+ | <a href="AAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAA.HTM">AAA</a> +---------+---------+---------+---------+---------+---------+ | <a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM">AAS</a> |
| Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | =SS | | Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | AL,Ib | eAX,Iv | =CS | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC</a> general register | <a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a> general register |
4|---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| eAX | eCX | eDX | eBX | eSP | eBP | eSI | eDI | eAX | eCX | eDX | eBX | eSP | eBP | eSI | eDI |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> general register | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> into general register |
5|---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| eAX | eCX | eDX | eBX | eSP | eBP | eSI | eDI | eAX | eCX | eDX | eBX | eSP | eBP | eSI | eDI |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> | <a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM">ARPL</a> | SEG | SEG | Operand| Address| <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="IMUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IMUL.HTM">IMUL</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="IMUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IMUL.HTM">IMUL</a> | <a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INSB</a> | <a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INSW/D</a> | <a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTSB</a> |<a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTSW/D</a> |
6| <a href="PUSHA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHA.HTM">PUSHA</a> | <a href="POPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPA.HTM">POPA</a> | | | | | | | | | | | | | | |
| | | Gv,Ma | Ew,Rw | =FS | =GS | Size | Size | Ib | GvEvIv | Ib | GvEvIv | Yb,DX | Yb,DX | Dx,Xb | DX,Xv |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Short displacement jump of condition (Jb) | Short-displacement jump on condition(Jb) |
7|---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JO</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNO</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JB</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNB</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JZ</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNZ</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JBE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNBE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JS</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNS</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JP</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNP</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JL</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNL</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JLE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNLE</a> |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Immediate Grpl | | Grpl | <a href="TEST.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TEST.HTM">TEST</a> | <a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a> | <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> | <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> | <a href="LEA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEA.HTM">LEA</a> | <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> |
8|---------+---------+ | +---------+---------+--------+--------+---------+---------+---------+---------+ | | | |
| Eb,Ib | Ev,Iv | | Ev,Iv | Eb,Gb | Ev,Gv | Eb,Gb | Ev,Gv | Eb,Gb | Ev,Gv | Gb,Eb | Gv,Ev | Ew,Sw | Gv,M | Sw,Ew | Ev |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | <a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a> word or double-word register with eAX | | | <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> | | <a href="PUSHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHF.HTM">PUSHF</a> | <a href="POPF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPF.HTM">POPF</a> | | |
9| <a href="NOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOP.HTM">NOP</a> +---------+---------+---------+---------+---------+--------+--------+ <a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM">CBW</a> | <a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM">CWD</a> | | <a href="WAIT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/WAIT.HTM">WAIT</a> | | | <a href="SAHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAHF.HTM">SAHF</a> | <a href="LAHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAHF.HTM">LAHF</a> |
| | eCX | eDX | eBX | eSP | eBP | eSI | eDI | | | Ap | | Fv | Fv | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> | <a href="MOVS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVS.HTM">MOVSB</a> | <a href="MOVS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVS.HTM">MOVSW/D</a> | <a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM">CMPSB</a> |<a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM">CMPSW/D</a> | <a href="TEST.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TEST.HTM">TEST</a> | <a href="STOS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STOS.HTM">STOSB</a> | <a href="STOS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STOS.HTM">STOSW/D</a> | <a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM">LODSB</a> | <a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM">LODSW/D</a> | <a href="SCAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SCAS.HTM">SCASB</a> |<a href="SCAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SCAS.HTM">SCASW/D</a> |
A|---------+---------+---------+---------+ | | | +---------+---------+ | | | | | |
| AL,Ob | eAX,Ov | Ob,AL | Ov,eAX | Xb,Yb | Xv,Yv | Xb,Yb | Xv,Yv | AL,Ib | eAX,Iv | Yb,AL | Yv,eAX | AL,Xb | eAX,Xv | AL,Xb |eAX,Xv |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> immediate byte into byte register | <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> immediate word or double into word or double register |
B|---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| AL | CL | DL | BL | AH | CH | DH | BH | eAX | eCX | eDX | eBX | eSP | eBP | eSI | eDI |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Shift Grp2 | <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> near | <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LES</a> | <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> | <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> | <a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM">ENTER</a> | | <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> far | <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> | <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> | | |
C|---------+---------+---------+---------+ | +--------+--------+ | <a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM">LEAVE</a> +---------+---------+ | | <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INTO</a> | <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> |
| Eb,Ib | Ev,Iv | Iw | | Gv,Mp | Gv,Mp | Eb,Ib | Ev,Iv | Iw,Ib | | Iw | | 3 | Ib | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Shift Grp2 | | | | | |
D|---------+---------+---------+---------+ <a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM">AAM</a> | <a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM">AAD</a> | | <a href="XLAT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XLAT.HTM">XLAT</a> | ESC(Escape to coprocessor instruction set) |
| Eb,1 | Ev,1 | Eb,CL | Ev,CL | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+-----------------------------+-------------------+-----------------+
| <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNE</a> | <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPE</a> | <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a> | <a href="IN.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IN.HTM">IN</a> | <a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM">OUT</a> | <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNP</a> | <a href="IN.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IN.HTM">IN</a> | <a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM">OUT</a> |
E| | | | +---------+---------+--------+--------+ +---------+---------+---------+---------+---------+--------+--------+
| Jb | Jb | Jb | Jb | AL,Ib | eAX,Ib | Ib,AL | Ib,eAX | Av | Jv | Ap | Jb | AL,DX | eAX,DX | DX,AL | DX,eAX |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REP</a> | | | Unary Grp3 | | | | | | |<a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC</a>/<a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a> |Indirct |
F| <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> | | <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REPNE</a> | | <a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM">HLT</a> | <a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM">CMC</a> +--------+--------+ <a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM">CLC</a> | <a href="STC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STC.HTM">STC</a> | <a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI</a> | <a href="STI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STI.HTM">STI</a> | <a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM">CLD</a> | <a href="STD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STD.HTM">STD</a> | | |
| | | | <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REPE</a> | | | Eb | Ev | | | | | | | Grp4 | Grp5 |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
</pre>
<h3>Two-Byte Opcode Map (first byte is 0FH)</h3>
<pre>
0 1 2 3 4 5 6 7 8 9 A B C D E F
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | <a href="LAR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAR.HTM">LAR</a> | <a href="LSL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LSL.HTM">LSL</a> | | | | | | | | | | | | |
0| Grp6 | Grp7 | | | | | <a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM">CLTS</a> | | | | | | | | | |
| | | Gw,Ew | Gv,Ew | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
1| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | | <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> | | | | | | | | | |
2| | | | | | | | | | | | | | | | |
| Cd,Rd | Dd,Rd | Rd,Cd | Rd,Dd | Td,Rd | | Rd,Td | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
3| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
4| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
5| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
6| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
7| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Long-displacement jump on condition (Jv) | Long-displacement jump on condition (Jv) |
8|---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JO</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNO</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JB</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNB</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JZ</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNZ</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JBE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNBE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JS</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNS</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JP</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNP</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JL</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNL</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JLE</a> | <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JNLE</a> |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| Byte Set on condition (Eb) | | | | | | | | |
9|---------+---------+---------+---------+---------+---------+--------+--------+ <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETS</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNS</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETP</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNP</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETL</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNL</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETLE</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNLE</a> |
| <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETO</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNO</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETB</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNB</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETZ</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNZ</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETBE</a> | <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETNBE</a> | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> | | <a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM">BT</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHLD</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHLD</a> | | | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> | | <a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHRD</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHRD</a> | | <a href="IMUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IMUL.HTM">IMUL</a> |
A| | | | | | | | | | | | | | | | |
| FS | FS | | Ev,Gv | EvGvIb | EvGvCL | | | GS | GS | | Ev,Gv | EvGvIb | EvGvCL | | Gv,Ev |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a> | <a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM">BTR</a> | <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a> | <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a> | <a href="MOVZX.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVZX.HTM">MOVZX</a> | | | Grp-8 | <a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM">BTC</a> | <a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM">BSF</a> | <a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM">BSR</a> | <a href="MOVSX.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVSX.HTM">MOVSX</a> |
B| | | | | | +--------+--------+ | | | | | +-----------------+
| | | Mp | Ev,Gv | Mp | Mp | Gv,Eb | Gv,Ew | | | Ev,Ib | Ev,Gv | Gv,Ev | Gv,Ev | Gv,Eb Gv,Ew |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
C| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
D| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
E| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
| | | | | | | | | | | | | | | | |
F| | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | |
+---------+---------+---------+---------+---------+---------+--------+--------+---------+---------+---------+---------+---------+---------+--------+--------+
</pre>
<h3>Opcodes determined by bits 5,4,3 of modR/M byte</h3>
<pre>
G +-------+-------+-------+
r | mod | nnn | R/M |
o +-------+-------+-------+
u
p 000 001 010 011 100 101 110 111
+-------+-------+-------+-------+-------+-------+-------+-------+
1| <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> | <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a> | <a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM">ADC</a> | <a href="SBB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SBB.HTM">SBB</a> | <a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND</a> | <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> | <a href="XOR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XOR.HTM">XOR</a> | <a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM">CMP</a> |
| | | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
2| <a href="RCL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RCL.HTM">ROL</a> | <a href="RCL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RCL.HTM">ROR</a> | <a href="RCL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RCL.HTM">RCL</a> | <a href="RCL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RCL.HTM">RCR</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHL</a> | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SHR</a> | | <a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SAR</a> |
| | | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
3| <a href="TEST.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TEST.HTM">TEST</a> | | <a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM">NOT</a> | <a href="NEG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NEG.HTM">NEG</a> | <a href="MUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MUL.HTM">MUL</a> | <a href="IMUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IMUL.HTM">IMUL</a> | <a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM">DIV</a> | <a href="IDIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IDIV.HTM">IDIV</a> |
| Ib/Iv | | | |AL/eAX |AL/eAX |AL/eAX |AL/eAX |
+-------+-------+-------+-------+-------+-------+-------+-------+
4| INC | <a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a> | | | | | | |
| Eb | Eb | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
5| <a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC</a> | <a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a> | <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> | <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> | <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> | <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> | <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> | |
| Ev | Ev | Ev | eP | Ev | Ep | Ev | |
+-------+-------+-------+-------+-------+-------+-------+-------+
</pre>
<h3>Opcodes determined by bits 5,4,3 of modR/M byte</h3>
<pre>
G +-------+-------+-------+
r | mod | nnn | R/M |
o +-------+-------+-------+
u
p 000 001 010 011 100 101 110 111
+-------+-------+-------+-------+-------+-------+-------+-------+
6| <a href="SLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SLDT.HTM">SLDT</a> | <a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR</a> | <a href="LLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LLDT.HTM">LLDT</a> | <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> | <a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERR</a> | <a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERW</a> | | |
| Ew | Ew | Ew | Ew | Ew | Ew | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
7| <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SGDT</a> | <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> | <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LGDT</a> | <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> | <a href="SMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SMSW.HTM">SMSW</a> | | <a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM">LMSW</a> | |
| Ms | Ms | Ms | Ms | Ew | | Ew | |
+-------+-------+-------+-------+-------+-------+-------+-------+
8| | | | | <a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM">BT</a> | <a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS</a> | <a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM">BTR</a> | <a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM">BTC</a> |
| | | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
</pre>
<p>
<hr>
<p><b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>next:</b> <a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 17</title>
</head>
<body>
<b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPA.HTM">Appendix A -- Opcode Map</a><br>
<b>next:</b> <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
<p>
<hr>
<p>
<h1>Appendix B -- Complete Flag Cross-Reference</h1>
<h3>Key to Codes</h3>
<pre>
T = instruction tests flag
M = instruction modifies flag
(either sets or resets depending on operands)
0 = instruction resets flag
1 = instruction sets flag
-- = instruction's effect on flag is undefined
R = instruction restores prior value of flag
blank = instruction does not affect flag
</pre>
<pre>
Instruction OF SF ZF AF PF CF TF IF DF NT RF
AAA -- -- -- TM -- M
AAD -- M M -- M --
AAM -- M M -- M --
AAS -- -- -- TM -- M
ADC M M M M M TM
ADD M M M M M M
AND 0 M M -- M 0
ARPL M
BOUND
BSF/BSR -- -- M -- -- --
BT/BTS/BTR/BTC -- -- -- -- -- M
CALL
CBW
CLC 0
CLD 0
CLI 0
CLTS
CMC M
CMP M M M M M M
CMPS M M M M M M T
CWD
DAA -- M M TM M TM
DAS -- M M TM M TM
DEC M M M M M
DIV -- -- -- -- -- --
ENTER
ESC
HLT
IDIV -- -- -- -- -- --
IMUL M -- -- -- -- M
IN
INC M M M M M
INS T
INT 0 0
INTO T 0 0
IRET R R R R R R R R R T
Jcond T T T T T
JCXZ
JMP
LAHF
LAR M
LDS/LES/LSS/LFS/LGS
LEA
LEAVE
LGDT/LIDT/LLDT/LMSW
LOCK
LODS T
LOOP
LOOPE/LOOPNE T
LSL M
LTR
MOV
MOV control, debug -- -- -- -- -- --
MOVS T
MOVSX/MOVZX
MUL M -- -- -- -- M
NEG M M M M M M
NOP
NOT
OR 0 M M -- M 0
OUT
OUTS T
POP/POPA
POPF R R R R R R R R R R
PUSH/PUSHA/PUSHF
RCL/RCR 1 M TM
RCL/RCR count -- TM
REP/REPE/REPNE
RET
ROL/ROR 1 M M
ROL/ROR count -- M
SAHF R R R R R
SAL/SAR/SHL/SHR 1 M M M -- M M
SAL/SAR/SHL/SHR count -- M M -- M M
SBB M M M M M TM
SCAS M M M M M M T
SET cond T T T T T
SGDT/SIDT/SLDT/SMSW
SHLD/SHRD -- M M -- M M
STC 1
STD 1
STI 1
STOS T
STR
SUB M M M M M M
TEST 0 M M -- M 0
VERR/VERRW M
WAIT
XCHG
XLAT
XOR 0 M M -- M 0
</pre>
<p>
<hr>
<p><b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPA.HTM">Appendix A -- Opcode Map</a><br>
<b>next:</b> <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Appendix C</title>
</head>
<body>
<b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
<b>next:</b> <a href="APPD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPD.HTM">Appendix D -- Condition Codes</a>
<p>
<hr>
<p>
<h1>Appendix C -- Status Flag Summary</h1>
<h3>Status Flags' Functions</h3>
<pre>
Bit Name Function
0 CF Carry Flag -- Set on high-order bit carry or borrow; cleared
otherwise.
2 PF Parity Flag -- Set if low-order eight bits of result contain
an even number of 1 bits; cleared otherwise.
4 AF Adjust flag -- Set on carry from or borrow to the low order
four bits of AL; cleared otherwise. Used for decimal
arithmetic.
6 ZF Zero Flag -- Set if result is zero; cleared otherwise.
7 SF Sign Flag -- Set equal to high-order bit of result (0 is
positive, 1 if negative).
11 OF Overflow Flag -- Set if result is too large a positive number
or too small a negative number (excluding sign-bit) to fit in
destination operand; cleared otherwise.
</pre>
<h3>Key to Codes</h3>
<pre>
T = instruction tests flag
M = instruction modifies flag
(either sets or resets depending on operands)
0 = instruction resets flag
-- = instruction's effect on flag is undefined
blank = instruction does not affect flag
</pre>
<pre>
Instruction OF SF ZF AF PF CF
AAA -- -- -- TM -- M
AAS -- -- -- TM -- M
AAD -- M M -- M --
AAM -- M M -- M --
DAA -- M M TM M TM
DAS -- M M TM M TM
ADC M M M M M TM
ADD M M M M M M
SBB M M M M M TM
SUB M M M M M M
CMP M M M M M M
CMPS M M M M M M
SCAS M M M M M M
NEG M M M M M M
DEC M M M M M
INC M M M M M
IMUL M -- -- -- -- M
MUL M -- -- -- -- M
RCL/RCR 1 M TM
RCL/RCR count -- TM
ROL/ROR 1 M M
ROL/ROR count -- M
SAL/SAR/SHL/SHR 1 M M M -- M M
SAL/SAR/SHL/SHR count -- M M -- M M
SHLD/SHRD -- M M -- M M
BSF/BSR -- -- M -- -- --
BT/BTS/BTR/BTC -- -- -- -- -- M
AND 0 M M -- M 0
OR 0 M M -- M 0
TEST 0 M M -- M 0
XOR 0 M M -- M 0
</pre>
<p>
<hr>
<p><b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
<b>next:</b> <a href="APPD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPD.HTM">Appendix D -- Condition Codes</a>
</body>

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<html>
<head>
<title>80386 Programmer's Reference Manual -- Appendix D</title>
</head>
<body>
<b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
<p>
<hr>
<p>
<h1>Appendix D -- Condition Codes</h1>
<em>
<h3>Note</h3>
The terms &quot;above&quot; and &quot;below&quot; refer to the relation between two unsigned values (neither SF nor OF is tested). The terms &quot;greater&quot; and &quot;less&quot; refer to the relation between two signed values (SF and OF are tested). </em>
<h3>Definition of Conditions</h3>
(For conditional instructions Jcond, and SETcond)
<pre>
Instruction Condition
Mnemonic Meaning Subcode Tested
O Overflow 0000 OF = 1
NO No overflow 0001 OF = 0
B Below
NAE Neither above nor equal 0010 CF = 1
NB Not below
AE Above or equal 0011 CF = 0
E Equal
Z Zero 0100 ZF = 1
NE Not equal
NZ Not zero 0101 ZF = 0
BE Below or equal
NA Not above 0110 (CF or ZF) = 1
NBE Neither below nor equal
NA Above 0111 (CF or ZF) = 0
S Sign 1000 SF = 1
NS No sign 1001 SF = 0
P Parity
PE Parity even 1010 PF = 1
NP No parity
PO Parity odd 1011 PF = 0
L Less
NGE Neither greater nor equal 1100 (SF xor OF) = 1
NL Not less
GE Greater or equal 1101 (SF xor OF) = 0
LE Less or equal
NG Not greater 1110 ((SF xor OF) or ZF) = 1
NLE Neither less nor equal
G Greater 1111 ((SF xor OF) or ZF) = 0
</pre>
<p>
<hr>
<p><b>up:</b> <a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a><br>
<b>prev:</b> <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode ARPL</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM"> AND Logical AND</a><br>
<b>next:</b><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM"> BOUND Check Array Index Against Bounds</a>
<p>
<hr>
<p>
<h1>ARPL -- Adjust RPL Field of Selector</h1>
<pre>
Opcode Instruction Clocks Description
63 /r ARPL r/m16,r16 pm=20/21 Adjust RPL of r/m16 to not
less than RPL of r16
</pre>
<h2>Operation</h2>
<pre>
IF RPL bits(0,1) of DEST &lt; RPL bits(0,1) of SRC
THEN
ZF := 1;
RPL bits(0,1) of DEST := RPL bits(0,1) of SRC;
ELSE
ZF := 0;
FI;
</pre>
<h2>Description</h2>
The ARPL instruction has two operands. The first operand is a 16-bit memory variable or word register that contains the value of a selector. The second operand is a word register. If the RPL field (&quot;requested privilege level&quot;--bottom two bits) of the first operand is less than the RPL field of the second operand, the zero flag is set to 1 and the RPL field of the first operand is increased to match the second operand. Otherwise, the zero flag is set to 0 and no change is made to the first operand.
<p>ARPL appears in operating system software, not in application programs. It is used to guarantee that a selector parameter to a subroutine does not request more privilege than the caller is allowed. The second operand of ARPL is normally a register that contains the CS selector value of the caller.
<h2>Flags Affected</h2>
ZF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 6; ARPL is not recognized in Real Address Mode
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM"> AND Logical AND</a><br>
<b>next:</b><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM"> BOUND Check Array Index Against Bounds</a>
</body>

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<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BOUND</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM"> ARPL Adjust RPL Field of Selector</a><br>
<b>next:</b><a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM"> BSF Bit Scan Forward</a>
<p>
<hr>
<p>
<h1>BOUND -- Check Array Index Against Bounds</h1>
<pre>
Opcode Instruction Clocks Description
62 /r BOUND r16,m16&16 10 Check if r16 is within bounds
(passes test)
62 /r BOUND r32,m32&32 10 Check if r32 is within bounds
(passes test)
</pre>
<h2>Operation</h2>
<pre>
IF (LeftSRC &lt; [RightSRC] OR LeftSRC &gt; [RightSRC + OperandSize/8])
(* Under lower bound or over upper bound *)
THEN Interrupt 5;
FI;
</pre>
<h2>Description</h2>
BOUND ensures that a signed array index is within the limits specified by a block of memory consisting of an upper and a lower bound. Each bound uses one word for an operand-size attribute of 16 bits and a doubleword for an operand-size attribute of 32 bits. The first operand (a register) must be greater than or equal to the first bound in memory (lower bound), and less than or equal to the second bound in memory (upper bound). If the register is not within bounds, an Interrupt 5 occurs; the return EIP points to the BOUND instruction.
<p>The bounds limit data structure is usually placed just before the array itself, making the limits addressable via a constant offset from the beginning of the array.
<h2>Flags Affected</h2>
None
<h2>Protected Mode Exceptions</h2>
Interrupt 5 if the bounds test fails, as described above; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<p>The second operand must be a memory operand, not a register. If BOUND is executed with a ModRM byte representing a register as the second operand, #UD occurs.
<h2>Real Address Mode Exceptions</h2>
Interrupt 5 if the bounds test fails; Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH; Interrupt 6 if the second operand is a register
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM"> ARPL Adjust RPL Field of Selector</a><br>
<b>next:</b><a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM"> BSF Bit Scan Forward</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BSF</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM"> BOUND Check Array Index Against Bounds</a><br>
<b>next:</b><a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM"> BSR Bit Scan Reverse</a>
<p>
<hr>
<p>
<h1>BSF -- Bit Scan Forward</h1>
<pre>
Opcode Instruction Clocks Description
0F BC BSF r16,r/m16 10+3n Bit scan forward on r/m word
0F BC BSF r32,r/m32 10+3n Bit scan forward on r/m dword
</pre>
<h2>Notes</h2>
is the number of leading zero bits.
<h2>Operation</h2>
<pre>
IF r/m = 0
THEN
ZF := 1;
register := UNDEFINED;
ELSE
temp := 0;
ZF := 0;
WHILE BIT[r/m, temp = 0]
DO
temp := temp + 1;
register := temp;
OD;
FI;
</pre>
<h2>Description</h2>
BSF scans the bits in the second word or doubleword operand starting with bit 0. The ZF flag is cleared if the bits are all 0; otherwise, the ZF flag is set and the destination register is loaded with the bit index of the first set bit.
<h2>Flags Affected</h2>
ZF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM"> BOUND Check Array Index Against Bounds</a><br>
<b>next:</b><a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM"> BSR Bit Scan Reverse</a>
</body>

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<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BSR</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM"> BSF Bit Scan Forward</a><br>
<b>next:</b><a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM"> BT Bit Test</a>
<p>
<hr>
<p>
<h1>BSR -- Bit Scan Reverse</h1>
<pre>
Opcode Instruction Clocks Description
0F BD BSR r16,r/m16 10+3n Bit scan reverse on r/m word
0F BD BSR r32,r/m32 10+3n Bit scan reverse on r/m dword
</pre>
<h2>Operation</h2>
<pre>
IF r/m = 0
THEN
ZF := 1;
register := UNDEFINED;
ELSE
temp := OperandSize - 1;
ZF := 0;
WHILE BIT[r/m, temp] = 0
DO
temp := temp - 1;
register := temp;
OD;
FI;
</pre>
<h2>Description</h2>
BSR scans the bits in the second word or doubleword operand from the most significant bit to the least significant bit. The ZF flag is cleared if the bits are all 0; otherwise, ZF is set and the destination register is loaded with the bit index of the first set bit found when scanning in the reverse direction.
<h2>Flags Affected</h2>
ZF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM"> BSF Bit Scan Forward</a><br>
<b>next:</b><a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM"> BT Bit Test</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BT</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM"> BSR Bit Scan Reverse</a><br>
<b>next:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a>
<p>
<hr>
<p>
<h1>BT -- Bit Test</h1>
<pre>
Opcode Instruction Clocks Description
0F A3 BT r/m16,r16 3/12 Save bit in carry flag
0F A3 BT r/m32,r32 3/12 Save bit in carry flag
0F BA /4 ib BT r/m16,imm8 3/6 Save bit in carry flag
0F BA /4 ib BT r/m32,imm8 3/6 Save bit in carry flag
</pre>
<h2>Operation</h2>
<pre>
CF := BIT[LeftSRC, RightSRC];
</pre>
<h2>Description</h2>
BT saves the value of the bit indicated by the base (first operand) and the bit offset (second operand) into the carry flag.
<h2>Flags Affected</h2>
CF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<h2>Notes</h2>
The index of the selected bit can be given by the immediate constant in the instruction or by a value in a general register. Only an 8-bit immediate value is used in the instruction. This operand is taken modulo 32, so the range of immediate bit offsets is 0..31. This allows any bit within a register to be selected. For memory bit strings, this immediate field gives only the bit offset within a word or doubleword. Immediate bit offsets larger than 31 are supported by using the immediate bit offset field in combination with the displacement field of the memory operand. The low-order 3 to 5 bits of the immediate bit offset are stored in the immediate bit offset field, and the high-order 27 to 29 bits are shifted and combined with the byte displacement in the addressing mode.
<p>When accessing a bit in memory, the 80386 may access four bytes starting from the memory address given by:
<pre>
Effective Address + (4 * (BitOffset DIV 32))
</pre>
for a 32-bit operand size, or two bytes starting from the memory address given by:
<pre>
Effective Address + (2 * (BitOffset DIV 16))
</pre>
for a 16-bit operand size. It may do so even when only a single byte needs to be accessed in order to reach the given bit. You must therefore avoid referencing areas of memory close to address space holes. In particular, avoid references to memory-mapped I/O registers. Instead, use the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM"> BSR Bit Scan Reverse</a><br>
<b>next:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BTC</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM"> BT Bit Test</a><br>
<b>next:</b><a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM"> BTR Bit Test and Reset</a>
<p>
<hr>
<p>
<h1>BTC -- Bit Test and Complement</h1>
<pre>
Opcode Instruction Clocks Description
0F BB BTC r/m16,r16 6/13 Save bit in carry flag and complement
0F BB BTC r/m32,r32 6/13 Save bit in carry flag and complement
0F BA /7 ib BTC r/m16,imm8 6/8 Save bit in carry flag and complement
0F BA /7 ib BTC r/m32,imm8 6/8 Save bit in carry flag and complement
</pre>
<h2>Operation</h2>
<pre>
CF := BIT[LeftSRC, RightSRC];
BIT[LeftSRC, RightSRC] := NOT BIT[LeftSRC, RightSRC];
</pre>
<h2>Description</h2>
BTC saves the value of the bit indicated by the base (first operand) and the bit offset (second operand) into the carry flag and then complements the bit.
<h2>Flags Affected</h2>
CF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<h2>Notes</h2>
The index of the selected bit can be given by the immediate constant in the instruction or by a value in a general register. Only an 8-bit immediate value is used in the instruction. This operand is taken modulo 32, so the range of immediate bit offsets is 0..31. This allows any bit within a register to be selected. For memory bit strings, this immediate field gives only the bit offset within a word or doubleword. Immediate bit offsets larger than 31 are supported by using the immediate bit offset field in combination with the displacement field of the memory operand. The low-order 3 to 5 bits of the immediate bit offset are stored in the immediate bit offset field, and the high-order 27 to 29 bits are shifted and combined with the byte displacement in the addressing mode.
<p>When accessing a bit in memory, the 80386 may access four bytes starting from the memory address given by:
<pre>
Effective Address + (4 * (BitOffset DIV 32))
</pre>
for a 32-bit operand size, or two bytes starting from the memory address given by:
<pre>
Effective Address + (2 * (BitOffset DIV 16))
</pre>
for a 16-bit operand size. It may do so even when only a single byte needs to be accessed in order to reach the given bit. You must therefore avoid referencing areas of memory close to address space holes. In particular, avoid references to memory-mapped I/O registers. Instead, use the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM"> BT Bit Test</a><br>
<b>next:</b><a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM"> BTR Bit Test and Reset</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BTR</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a><br>
<b>next:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a>
<p>
<hr>
<p>
<h1>BTR -- Bit Test and Reset</h1>
<pre>
Opcode Instruction Clocks Description
0F B3 BTR r/m16,r16 6/13 Save bit in carry flag and reset
0F B3 BTR r/m32,r32 6/13 Save bit in carry flag and reset
0F BA /6 ib BTR r/m16,imm8 6/8 Save bit in carry flag and reset
0F BA /6 ib BTR r/m32,imm8 6/8 Save bit in carry flag and reset
</pre>
<h2>Operation</h2>
<pre>
CF := BIT[LeftSRC, RightSRC];
BIT[LeftSRC, RightSRC] := 0;
</pre>
<h2>Description</h2>
BTR saves the value of the bit indicated by the base (first operand) and the bit offset (second operand) into the carry flag and then stores 0 in the bit.
<h2>Flags Affected</h2>
CF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<h2>Notes</h2>
The index of the selected bit can be given by the immediate constant in the instruction or by a value in a general register. Only an 8-bit immediate value is used in the instruction. This operand is taken modulo 32, so the range of immediate bit offsets is 0..31. This allows any bit within a register to be selected. For memory bit strings, this immediate field gives only the bit offset within a word or doubleword. Immediate bit offsets larger than 31 (or 15) are supported by using the immediate bit offset field in combination with the displacement field of the memory operand. The low-order 3 to 5 bits of the immediate bit offset are stored in the immediate bit offset field, and the high-order 27 to 29 bits are shifted and combined with the byte displacement in the addressing mode.
<p>When accessing a bit in memory, the 80386 may access four bytes starting from the memory address given by:
<pre>
Effective Address + 4 * (BitOffset DIV 32)
</pre>
for a 32-bit operand size, or two bytes starting from the memory address given by:
<pre>
Effective Address + 2 * (BitOffset DIV 16)
</pre>
for a 16-bit operand size. It may do so even when only a single byte needs to be accessed in order to reach the given bit. You must therefore avoid referencing areas of memory close to address space holes. In particular, avoid references to memory-mapped I/O registers. Instead, use the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a><br>
<b>next:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode BTS</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM"> BTR Bit Test and Reset</a><br>
<b>next:</b><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM"> CALL Call Procedure</a>
<p>
<hr>
<p>
<h1>BTS -- Bit Test and Set</h1>
<pre>
Opcode Instruction Clocks Description
0F AB BTS r/m16,r16 6/13 Save bit in carry flag and set
0F AB BTS r/m32,r32 6/13 Save bit in carry flag and set
0F BA /5 ib BTS r/m16,imm8 6/8 Save bit in carry flag and set
0F BA /5 ib BTS r/m32,imm8 6/8 Save bit in carry flag and set
</pre>
<h2>Operation</h2>
<pre>
CF := BIT[LeftSRC, RightSRC];
BIT[LeftSRC, RightSRC] := 1;
</pre>
<h2>Description</h2>
BTS saves the value of the bit indicated by the base (first operand) and the bit offset (second operand) into the carry flag and then stores 1 in the bit.
<h2>Flags Affected</h2>
CF as described above
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<h2>Notes</h2>
The index of the selected bit can be given by the immediate constant in the instruction or by a value in a general register. Only an 8-bit immediate value is used in the instruction. This operand is taken modulo 32, so the range of immediate bit offsets is 0..31. This allows any bit within a register to be selected. For memory bit strings, this immediate field gives only the bit offset within a word or doubleword. Immediate bit offsets larger than 31 are supported by using the immediate bit offset field in combination with the displacement field of the memory operand. The low-order 3 to 5 bits of the immediate bit offset are stored in the immediate bit offset field, and the high order 27 to 29 bits are shifted and combined with the byte displacement in the addressing mode.
<p>When accessing a bit in memory, the processor may access four bytes starting from the memory address given by:
<pre>
Effective Address + (4 * (BitOffset DIV 32))
</pre>
for a 32-bit operand size, or two bytes starting from the memory address given by:
<pre>
Effective Address + (2 * (BitOffset DIV 16))
</pre>
for a 16-bit operand size. It may do this even when only a single byte needs to be accessed in order to get at the given bit. Thus the programmer must be careful to avoid referencing areas of memory close to address space holes. In particular, avoid references to memory-mapped I/O registers. Instead, use the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM"> BTR Bit Test and Reset</a><br>
<b>next:</b><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM"> CALL Call Procedure</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 01</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>next:</b> <a href="S01_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_01.HTM">1.1 Organization of This Manual</a>
<p>
<hr>
<p>
<h1>Chapter 1 -- Introduction to the 80386</h1>
<p>The 80386 is an advanced 32-bit microprocessor optimized for multitasking operating systems and designed for applications needing very high performance. The 32-bit registers and data paths support 32-bit addresses and data types. The processor can address up to four gigabytes of physical memory and 64 terabytes (2^(46) bytes) of virtual memory. The on-chip memory-management facilities include address translation registers, advanced multitasking hardware, a protection mechanism, and paged virtual memory. Special debugging registers provide data and code breakpoints even in ROM-based software.
<p><a href="S01_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_01.HTM">1.1 Organization of This Manual</a><br>
<a href="S01_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_02.HTM">1.2 Related Literature</a><br>
<a href="S01_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_03.HTM">1.3 Notational Conventions</a><br>
<p>
<hr>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>next:</b> <a href="S01_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_01.HTM">1.1 Organization of This Manual</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 02</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S01_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_03.HTM">1.3 Notational Conventions</a><br>
<b>next:</b> <a href="S02_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_01.HTM">2.1 Memory Organization and Segmentation</a>
<p>
<hr>
<p>
<h1>Chapter 2 -- Basic Programming Model</h1>
<p>This chapter describes the 80386 application programming environment as seen by assembly language programmers when the processor is executing in protected mode. The chapter introduces programmers to those features of the 80386 architecture that directly affect the design and implementation of 80386 applications programs. Other chapters discuss 80386 features that relate to systems programming or to compatibility with other processors of the 8086 family.
<p>The basic programming model consists of these aspects:
<ul>
<li>Memory organization and segmentation
<li>Data types
<li>Registers
<li>Instruction format
<li>Operand selection
<li>Interrupts and exceptions
</ul>
Note that input/output is not included as part of the basic programming model. Systems designers may choose to make I/O instructions available to applications or may choose to reserve these functions for the operating system. For this reason, the I/O features of the 80386 are discussed in <a href="PII.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PII.HTM">Part II</a>.
<p>This chapter contains a section for each aspect of the architecture that is normally visible to applications.
<p><a href="S02_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_01.HTM">2.1 Memory Organization and Segmentation</a><br>
<a href="S02_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_02.HTM">2.2 Data Types</a><br>
<a href="S02_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_03.HTM">2.3 Registers</a><br>
<a href="S02_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_04.HTM">2.4 Instruction Format</a><br>
<a href="S02_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_05.HTM">2.5 Operand Selection</a><br>
<a href="S02_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_06.HTM">2.6 Interrupts and Exceptions</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S01_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_03.HTM">1.3 Notational Conventions</a><br>
<b>next:</b> <a href="S02_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_01.HTM">2.1 Memory Organization and Segmentation</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 03</title>
</head>
<body>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S02_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_06.HTM">2.6 Interrupts and Exceptions</a><br>
<b>next:</b> <a href="S03_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_01.HTM">3.1 Data Movement Instructions</a>
<p>
<hr>
<p>
<h1>Chapter 3 Applications Instruction Set</h1>
This chapter presents an overview of the instructions which programmers can use to write application software for the 80386 executing in protected virtual-address mode. The instructions are grouped by categories of related functions.
<p>The instructions not discussed in this chapter are those that are normally used only by operating-system programmers. Part II describes the operation of these instructions.
<p>The descriptions in this chapter assume that the 80386 is operating in protected mode with 32-bit addressing in effect; however, all instructions discussed are also available when 16-bit addressing is in effect in protected mode, real mode, or virtual 8086 mode. For any differences of operation that exist in the various modes , refer to <a href="C13.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C13.HTM">Chapter 13</a> , <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14</a> , or <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15</a> .
<p>The instruction dictionary in <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17</a> contains more detailed descriptions of all instructions, including encoding, operation, timing, effect on flags, and exceptions.
<p><a href="S03_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_01.HTM">3.1 Data Movement Instructions</a><br>
<a href="S03_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_02.HTM">3.2 Binary Arithmetic Instructions</a><br>
<a href="S03_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_03.HTM">3.3 Decimal Arithmetic Instructions</a><br>
<a href="S03_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_04.HTM">3.4 Logical Instructions</a><br>
<a href="S03_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_05.HTM">3.5 Control Transfer Instructions</a><br>
<a href="S03_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_06.HTM">3.6 String and Character Translation Instructions</a><br>
<a href="S03_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_07.HTM">3.7 Instructions for Block-Structured Languages</a><br>
<a href="S03_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_08.HTM">3.8 Flag Control Instructions</a><br>
<a href="S03_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_09.HTM">3.9 Coprocessor Interface Instructions</a><br>
<a href="S03_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_10.HTM">3.10 Segment Register Instructions</a><br>
<a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S02_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_06.HTM">2.6 Interrupts and Exceptions</a><br>
<b>next:</b> <a href="S03_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_01.HTM">3.1 Data Movement Instructions</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 04</title>
</head>
<body>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a><br>
<b>next:</b> <a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a>
<p>
<hr>
<p>
<h1>Chapter 4 Systems Architecture</h1>
<p>Many of the architectural features of the 80386 are used only by systems programmers. This chapter presents an overview of these aspects of the architecture.
<p>The systems-level features of the 80386 architecture include:
<ul>
<li>Memory Management
<li>Protection
<li>Multitasking
<li>Input/Output
<li>Exceptions and Interrupts
<li>Initialization
<li>Coprocessing and Multiprocessing
<li>Debugging
</ul>
These features are implemented by registers and instructions, all of which are introduced in the following sections. The purpose of this chapter is not to explain each feature in detail, but rather to place the remaining chapters of Part II in perspective. Each mention in this chapter of a register or instruction is either accompanied by an explanation or a reference to a following chapter where detailed information can be obtained.
<p><a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a><br>
<a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a><br>
<b>next:</b> <a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 05</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a><br>
<b>next:</b> <a href="S05_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_01.HTM">5.1 Segment Translation</a>
<p>
<hr>
<p>
<h1>Chapter 5 Memory Management</h1>
<p>The 80386 transforms logical addresses (i.e., addresses as viewed by programmers) into physical address (i.e., actual addresses in physical memory) in two steps:
<ul>
<li>Segment translation, in which a logical address (consisting of a segment selector and segment offset) are converted to a linear address.
<li>Page translation, in which a linear address is converted to a physical address. This step is optional, at the discretion of systems-software designers.
</ul>
These translations are performed in a way that is not visible to applications programmers. <a href="#fig5-1">Figure 5-1</a> illustrates the two translations at a high level of abstraction.
<p><a href="#fig5-1">Figure 5-1</a> and the remainder of this chapter present a simplified view of the 80386 addressing mechanism. In reality, the addressing mechanism also includes memory protection features. For the sake of simplicity, however, the subject of protection is taken up in another chapter, <a href="C06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C06.HTM">Chapter 6</a>.
<p><a name="fig5-1"><img align="center" src="FIG5-1.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG5-1.GIF" border="0">
<p><a href="S05_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_01.HTM">5.1 Segment Translation</a><br>
<a href="S05_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_02.HTM">5.2 Page Translation</a><br>
<a href="S05_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_03.HTM">5.3 Combining Segment and Page Translation</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a><br>
<b>next:</b> <a href="S05_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_01.HTM">5.1 Segment Translation</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 06</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S05_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_03.HTM">5.3 Combining Segment and Page Translation</a><br>
<b>next:</b> <a href="S06_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_01.HTM">6.1 Why Protection?</a>
<p>
<hr>
<p>
<h1>Chapter 6 Protection</h1>
<p><a href="S06_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_01.HTM">6.1 Why Protection?</a><br>
<a href="S06_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_02.HTM">6.2 Overview of 80386 Protection Mechanisms</a><br>
<a href="S06_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_03.HTM">6.3 Segment-Level Protection</a><br>
<a href="S06_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_04.HTM">6.4 Page-Level Protection</a><br>
<a href="S06_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_05.HTM">6.5 Combining Page and Segment Protection</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S05_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_03.HTM">5.3 Combining Segment and Page Translation</a><br>
<b>next:</b> <a href="S06_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_01.HTM">6.1 Why Protection?</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 07</title>
</head>
<body>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S06_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_05.HTM">6.5 Combining Page and Segment Protection</a><br>
<b>next:</b> <a href="S07_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_01.HTM">7.1 Task State Segment</a>
<p>
<hr>
<p>
<h1>Chapter 7 Multitasking</h1>
<p>To provide efficient, protected multitasking, the 80386 employs several special data structures. It does not, however, use special instructions to control multitasking; instead, it interprets ordinary control-transfer instructions differently when they refer to the special data structures. The registers and data structures that support multitasking are:
<ul>
<li>Task state segment
<li>Task state segment descriptor
<li>Task register
<li>Task gate descriptor
</ul>
With these structures the 80386 can rapidly switch execution from one task to another, saving the context of the original task so that the task can be restarted later. In addition to the simple task switch, the 80386 offers two other task-management features:
<ol>
<li>Interrupts and exceptions can cause task switches (if needed in the system design). The processor not only switches automatically to the task that handles the interrupt or exception, but it automatically switches back to the interrupted task when the interrupt or exception has been serviced. Interrupt tasks may interrupt lower-priority interrupt tasks to any depth.
<li>With each switch to another task, the 80386 can also switch to another LDT and to another page directory. Thus each task can have a different logical-to-linear mapping and a different linear-to-physical mapping. This is yet another protection feature, because tasks can be isolated and prevented from interfering with one another.
</ol>
<p><a href="S07_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_01.HTM">7.1 Task State Segment</a><br>
<a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a><br>
<a href="S07_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_03.HTM">7.3 Task Register</a><br>
<a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a><br>
<a href="S07_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_05.HTM">7.5 Task Switching</a><br>
<a href="S07_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_06.HTM">7.6 Task Linking</a><br>
<a href="S07_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_07.HTM">7.7 Task Address Space</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S06_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_05.HTM">6.5 Combining Page and Segment Protection</a><br>
<b>next:</b> <a href="S07_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_01.HTM">7.1 Task State Segment</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 08</title>
</head>
<body>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S07_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_07.HTM">7.7 Task Address Space</a><br>
<b>next:</b> <a href="S08_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_01.HTM">8.1 I/O Addressing</a>
<p>
<hr>
<p>
<h1>Chapter 8 Input/Output</h1>
<p>This chapter presents the I/O features of the 80386 from the following perspectives:
<ul>
<li>Methods of addressing I/O ports
<li>Instructions that cause I/O operations
<li>Protection as it applies to the use of I/O instructions and I/O port addresses.
</ul>
<p><a href="S08_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_01.HTM">8.1 I/O Addressing</a><br>
<a href="S08_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_02.HTM">8.2 I/O Instructions</a><br>
<a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S07_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_07.HTM">7.7 Task Address Space</a><br>
<b>next:</b> <a href="S08_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_01.HTM">8.1 I/O Addressing</a>
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<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 09</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a><br>
<b>next:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a>
<p>
<hr>
<p>
<h1>Chapter 9 Exceptions and Interrupts</h1>
<p>Interrupts and exceptions are special kinds of control transfer; they work somewhat like unprogrammed <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a>s. They alter the normal program flow to handle external events or to report errors or exceptional conditions. The difference between interrupts and exceptions is that interrupts are used to handle asynchronous events external to the processor, but exceptions handle conditions detected by the processor itself in the course of executing instructions.
<p>There are two sources for external interrupts and two sources for exceptions:
<ol>
<li>Interrupts
<ul>
<li>Maskable interrupts, which are signalled via the INTR pin.
<li>Nonmaskable interrupts, which are signalled via the NMI (Non-Maskable Interrupt) pin.
</ul>
<li>Exceptions
<ul>
<li>Processor detected. These are further classified as faults, traps, and aborts.
<li>Programmed. The instructions <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INTO</a>, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> 3, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a>, and <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> can trigger exceptions. These instructions are often called &quot;software interrupts&quot;, but the processor handles them as exceptions.
</ul>
</ol>
This chapter explains the features that the 80386 offers for controlling and responding to interrupts when it is executing in protected mode.
<p><a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a><br>
<a href="S09_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_02.HTM">9.2 Enabling and Disabling Interrupts</a><br>
<a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a><br>
<a href="S09_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM">9.4 Interrupt Descriptor Table</a><br>
<a href="S09_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_05.HTM">9.5 IDT Descriptors</a><br>
<a href="S09_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_06.HTM">9.6 Interrupt Tasks and Interrupt Procedures</a><br>
<a href="S09_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_07.HTM">9.7 Error Code</a><br>
<a href="S09_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_08.HTM">9.8 Exception Conditions</a><br>
<a href="S09_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_09.HTM">9.9 Exception Summary</a><br>
<a href="S09_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_10.HTM">9.10 Error Code Summary</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a><br>
<b>next:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 10</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S09_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_10.HTM">9.10 Error Code Summary</a><br>
<b>next:</b> <a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a>
<p>
<hr>
<p>
<h1>Chapter 10 Initialization</h1>
<p>After a signal on the RESET pin, certain registers of the 80386 are set to predefined values. These values are adequate to enable execution of a bootstrap program, but additional initialization must be performed by software before all the features of the processor can be utilized.
<p><a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a><br>
<a href="S10_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_02.HTM">10.2 Software Initialization for Real-Address Mode</a><br>
<a href="S10_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_03.HTM">10.3 Switching to Protected Mode</a><br>
<a href="S10_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_04.HTM">10.4 Software Initialization for Protected Mode</a><br>
<a href="S10_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_05.HTM">10.5 Initialization Example</a><br>
<a href="S10_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_06.HTM">10.6 TLB Testing</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S09_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_10.HTM">9.10 Error Code Summary</a><br>
<b>next:</b> <a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 11</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S10_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_06.HTM">10.6 TLB Testing</a><br>
<b>next:</b> <a href="S11_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_01.HTM">11.1 Coprocessing</a>
<p>
<hr>
<p>
<h1>Chapter 11 Coprocessing and Multiprocessing</h1>
<p>The 80386 has two levels of support for multiple parallel processing units:
<ul>
<li>A highly specialized interface for very closely coupled processors of a type known as coprocessors.
<li>A more general interface for more loosely coupled processors of unspecified type.
</ul>
<p><a href="S11_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_01.HTM">11.1 Coprocessing</a><br>
<a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S10_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_06.HTM">10.6 TLB Testing</a><br>
<b>next:</b> <a href="S11_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_01.HTM">11.1 Coprocessing</a>
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<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 12</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a><br>
<b>next:</b> <a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a>
<p>
<hr>
<p>
<h1>Chapter 12 Debugging</h1>
<p>The 80386 brings to Intel's line of microprocessors significant advances in debugging power. The single-step exception and breakpoint exception of previous processors are still available in the 80386, but the principal debugging support takes the form of debug registers. The debug registers support both instruction breakpoints and data breakpoints. Data breakpoints are an important innovation that can save hours of debugging time by pinpointing, for example, exactly when a data structure is being overwritten. The breakpoint registers also eliminate the complexities associated with writing a breakpoint instruction into a code segment (requires a data-segment alias for the code segment) or a code segment shared by multiple tasks (the breakpoint exception can occur in the context of any of the tasks). Breakpoints can even be set in code contained in ROM.
<p><a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a><br>
<a href="S12_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_02.HTM">12.2 Debug Registers</a><br>
<a href="S12_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_03.HTM">12.3 Debug Exceptions</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a><br>
<b>next:</b> <a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 13</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S12_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_03.HTM">12.3 Debug Exceptions</a><br>
<b>next:</b> <a href="S13_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_01.HTM">13.1 80286 Code Executes as a Subset of the 80386</a>
<p>
<hr>
<p>
<h1>Chapter 13 Executing 80286 Protected-Mode Code</h1>
<p><a href="S13_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_01.HTM">13.1 80286 Code Executes as a Subset of the 80386</a><br>
<a href="S13_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_02.HTM">13.2 Two ways to Execute 80286 Tasks</a><br>
<a href="S13_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_03.HTM">13.3 Differences From 80286</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S12_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_03.HTM">12.3 Debug Exceptions</a><br>
<b>next:</b> <a href="S13_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_01.HTM">13.1 80286 Code Executes as a Subset of the 80386</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 14</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S13_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_03.HTM">13.3 Differences From 80286</a><br>
<b>next:</b> <a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a>
<p>
<hr>
<p>
<h1>Chapter 14 80386 Real-Address Mode</h1>
<p>The real-address mode of the 80386 executes object code designed for execution on 8086, 8088, 80186, or 80188 processors, or for execution in the real-address mode of an 80286:
<p>In effect, the architecture of the 80386 in this mode is almost identical to that of the 8086, 8088, 80186, and 80188. To a programmer, an 80386 in real-address mode appears as a high-speed 8086 with extensions to the instruction set and registers. The principal features of this architecture are defined in <a href="C02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C02.HTM">Chapters 2</a> and <a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">3</a>.
<p>This chapter discusses certain additional topics that complete the system programmer's view of the 80386 in real-address mode:
<ul>
<li>Address formation.
<li>Extensions to registers and instructions.
<li>Interrupt and exception handling.
<li>Entering and leaving real-address mode.
<li>Real-address-mode exceptions.
<li>Differences from 8086.
<li>Differences from 80286 real-address mode.
</ul>
<p><a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a><br>
<a href="S14_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_02.HTM">14.2 Registers and Instructions</a><br>
<a href="S14_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_03.HTM">14.3 Interrupt and Exception Handling</a><br>
<a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a><br>
<a href="S14_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_05.HTM">14.5 Switching Back to Real-Address Mode</a><br>
<a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a><br>
<a href="S14_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_07.HTM">14.7 Differences From 8086</a><br>
<a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S13_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_03.HTM">13.3 Differences From 80286</a><br>
<b>next:</b> <a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 15</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a><br>
<b>next:</b> <a href="S15_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_01.HTM">15.1 Executing 8086 Code</a>
<p>
<hr>
<p>
<h1>Chapter 15 Virtual 8086 Mode</h1>
<p>The 80386 supports execution of one or more 8086, 8088, 80186, or 80188 programs in an 80386 protected-mode environment. An 8086 program runs in this environment as part of a V86 (virtual 8086) task. V86 tasks take advantage of the hardware support of multitasking offered by the protected mode. Not only can there be multiple V86 tasks, each one executing an 8086 program, but V86 tasks can be multiprogrammed with other 80386 tasks.
<p>The purpose of a V86 task is to form a &quot;virtual machine&quot; with which to execute an 8086 program. A complete virtual machine consists not only of 80386 hardware but also of systems software. Thus, the emulation of an 8086 is the result of cooperation between hardware and software:
<ul>
<li>The hardware provides a virtual set of registers (via the TSS), a virtual memory space (the first megabyte of the linear address space of the task), and directly executes all instructions that deal with these registers and with this address space.
<li>The software controls the external interfaces of the virtual machine (I/O, interrupts, and exceptions) in a manner consistent with the larger environment in which it executes. In the case of I/O, software can choose either to emulate I/O instructions or to let the hardware execute them directly without software intervention.
</ul>
Software that helps implement virtual 8086 machines is called a V86 monitor.
<p><a href="S15_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_01.HTM">15.1 Executing 8086 Code</a><br>
<a href="S15_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_02.HTM">15.2 Structure of a V86 Task</a><br>
<a href="S15_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_03.HTM">15.3 Entering and Leaving V86 Mode</a><br>
<a href="S15_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_04.HTM">15.4 Additional Sensitive Instructions</a><br>
<a href="S15_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_05.HTM">15.5 Virtual I/O</a><br>
<a href="S15_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_06.HTM">15.6 Differences From 8086</a><br>
<a href="S15_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_07.HTM">15.7 Differences From 80286 Real-Address Mode</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a><br>
<b>next:</b> <a href="S15_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_01.HTM">15.1 Executing 8086 Code</a>
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<head>
<title>80386 Programmer's Reference Manual -- Chapter 16</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S15_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_07.HTM">15.7 Differences From 80286 Real-Address Mode</a><br>
<b>next:</b> <a href="S16_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_01.HTM">16.1 How the 80386 Implements 16-Bit and 32-Bit Features</a>
<p>
<hr>
<p>
<h1>Chapter 16 Mixing 16-Bit and 32 Bit Code</h1>
<p>The 80386 running in protected mode is a 32-bit microprocessor, but it is designed to support 16-bit processing at three levels:
<ol>
<li>Executing 8086/80286 16-bit programs efficiently with complete compatibility.
<li>Mixing 16-bit modules with 32-bit modules.
<li>Mixing 16-bit and 32-bit addresses and operands within one module.
</ol>
The first level of support for 16-bit programs has already been discussed in <a href="C13.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C13.HTM">Chapter 13</a>, <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14</a>, and <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15</a>. This chapter shows how 16-bit and 32-bit modules can cooperate with one another, and how one module can utilize both 16-bit and 32-bit operands and addressing.
<p>The 80386 functions most efficiently when it is possible to distinguish between pure 16-bit modules and pure 32-bit modules. A pure 16-bit module has these characteristics:
<ul>
<li>All segments occupy 64 Kilobytes or less.
<li>Data items are either 8 bits or 16 bits wide.
<li>Pointers to code and data have 16-bit offsets.
<li>Control is transferred only among 16-bit segments.
</ul>
A pure 32-bit module has these characteristics:
<ul>
<li>Segments may occupy more than 64 Kilobytes (zero bytes to 4 gigabytes).
<li>Data items are either 8 bits or 32 bits wide.
<li>Pointers to code and data have 32-bit offsets.
<li>Control is transferred only among 32-bit segments.
</ul>
Pure 16-bit modules do exist; they are the modules designed for 16-bit microprocessors. Pure 32-bit modules may exist in new programs designed explicitly for the 80386. However, as systems designers move applications from 16-bit processors to the 32-bit 80386, it will not always be possible to maintain these ideals of pure 16-bit or 32-bit modules. It may be expedient to execute old 16-bit modules in a new 32-bit environment without making source-code changes to the old modules if any of the following conditions is true:
<ul>
<li>Modules will be converted one-by-one from 16-bit environments to 32-bit environments.
<li>Older, 16-bit compilers and software-development tools will be utilized in the new32-bit operating environment until new 32-bit versions can be created.
<li>The source code of 16-bit modules is not available for modification.
<li>The specific data structures used by a given module inherently utilize 16-bit words.
<li>The native word size of the source language is 16 bits.
</ul>
On the 80386, 16-bit modules can be mixed with 32-bit modules. To design a system that mixes 16- and 32-bit code requires an understanding of the mechanisms that the 80386 uses to invoke and control its 32-bit and 16-bit features.
<p><a href="S16_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_01.HTM">16.1 How the 80386 Implements 16-Bit and 32-Bit Features</a><br>
<a href="S16_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_02.HTM">16.2 Mixing 32-Bit and 16-Bit Operations</a><br>
<a href="S16_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_03.HTM">16.3 Sharing Data Segments Among Mixed Code Segments</a><br>
<a href="S16_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_04.HTM">16.4 Transferring Control Among Mixed Code Segments</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S15_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_07.HTM">15.7 Differences From 80286 Real-Address Mode</a><br>
<b>next:</b> <a href="S16_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_01.HTM">16.1 How the 80386 Implements 16-Bit and 32-Bit Features</a>
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<html>
<head>
<title>80386 Programmer's Reference Manual -- Chapter 17</title>
</head>
<body>
<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S16_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_04.HTM">16.4 Transferring Control Among Mixed Code Segments&gt;</a><br>
<b>next:</b> <a href="S17_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_01.HTM">17.1 Operand-Size and Address-Size Attributes</a>
<p>
<hr>
<p>
<h1>Chapter 17 80386 Instruction Set</h1>
<p>This chapter presents instructions for the 80386 in alphabetical order. For each instruction, the forms are given for each operand combination, including object code produced, operands required, execution time, and a description. For each instruction, there is an operational description and a summary of exceptions generated.
<p><a href="S17_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_01.HTM">17.1 Operand-Size and Address-Size Attributes</a><br>
<a href="S17_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_02.HTM">17.2 Instruction Format</a>
<h2>Instruction Set</h2>
<a href="AAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAA.HTM">AAA ASCII Adjust after Addition</a><br>
<a href="AAD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAD.HTM">AAD ASCII Adjust AX before Division</a><br>
<a href="AAM.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAM.HTM">AAM ASCII Adjust AX after Multiply</a><br>
<a href="AAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AAS.HTM">AAS ASCII Adjust AL after Subtraction</a><br>
<a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM">ADC Add with Carry</a><br>
<a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD Add</a><br>
<a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND Logical AND</a><br>
<a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM">ARPL Adjust RPL Field of Selector</a><br>
<a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND Check Array Index Against Bounds</a><br>
<a href="BSF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSF.HTM">BSF Bit Scan Forward</a><br>
<a href="BSR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BSR.HTM">BSR Bit Scan Reverse</a><br>
<a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM">BT Bit Test</a><br>
<a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM">BTC Bit Test and Complement</a><br>
<a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM">BTR Bit Test and Reset</a><br>
<a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS Bit Test and Set</a><br>
<a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL Call Procedure</a><br>
<a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM">CBW/CWDE Convert Byte to Word/Convert Word to Doubleword</a><br>
<a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM">CLC Clear Carry Flag</a><br>
<a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM">CLD Clear Direction Flag</a><br>
<a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI Clear Interrupt Flag</a><br>
<a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM">CLTS Clear Task-Switched Flag in CR0</a><br>
<a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM">CMC Complement Carry Flag</a><br>
<a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM">CMP Compare Two Operands</a><br>
<a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM">CMPS/CMPSB/CMPSW/CMPSD Compare String Operands</a><br>
<a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM">CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword</a><br>
<a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM">DAA Decimal Adjust AL after Addition</a><br>
<a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM">DAS Decimal Adjust AL after Subtraction</a><br>
<a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC Decrement by 1</a><br>
<a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM">DIV Unsigned Divide</a><br>
<a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM">ENTER Make Stack Frame for Procedure Parameters</a><br>
<a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM">HLT Halt</a><br>
<a href="IDIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IDIV.HTM">IDIV Signed Divide</a><br>
<a href="IMUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IMUL.HTM">IMUL Signed Multiply</a><br>
<a href="IN.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IN.HTM">IN Input from Port</a><br>
<a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC Increment by 1</a><br>
<a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INS/INSB/INSW/INSD Input from Port to String</a><br>
<a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT/INTO Call to Interrupt Procedure</a><br>
<a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET/IRETD Interrupt Return</a><br>
<a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">Jcc Jump if Condition is Met</a><br>
<a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP Jump</a><br>
<a href="LAHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAHF.HTM">LAHF Load Flags into AH Register</a><br>
<a href="LAR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAR.HTM">LAR Load Access Rights Byte</a><br>
<a href="LEA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEA.HTM">LEA Load Effective Address</a><br>
<a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM">LEAVE High Level Procedure Exit</a><br>
<a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LGDT/LIDT Load Global/Interrupt Descriptor Table Register</a><br>
<a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS/LSS/LDS/LES/LFS Load Full Pointer</a><br>
<a href="LLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LLDT.HTM">LLDT Load Local Descriptor Table Register</a><br>
<a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM">LMSW Load Machine Status Word</a><br>
<a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK Assert LOCK# Signal Prefix</a><br>
<a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM">LODS/LODSB/LODSW/LODSD Load String Operand</a><br>
<a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP/LOOPcond Loop Control with CX Counter</a><br>
<a href="LSL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LSL.HTM">LSL Load Segment Limit</a><br>
<a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR Load Task Register</a><br>
<a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV Move Data</a><br>
<a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV Move to/from Special Registers</a><br>
<a href="MOVS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVS.HTM">MOVS/MOVSB/MOVSW/MOVSD Move Data from String to String</a><br>
<a href="MOVSX.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVSX.HTM">MOVSX Move with Sign-Extend</a><br>
<a href="MOVZX.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVZX.HTM">MOVZX Move with Zero-Extend</a><br>
<a href="MUL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MUL.HTM">MUL Unsigned Multiplication of AL or AX</a><br>
<a href="NEG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NEG.HTM">NEG Two's Complement Negation</a><br>
<a href="NOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOP.HTM">NOP No Operation</a><br>
<a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM">NOT One's Complement Negation</a><br>
<a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR Logical Inclusive OR</a><br>
<a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM">OUT Output to Port</a><br>
<a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTS/OUTSB/OUTSW/OUTSD Output String to Port</a><br>
<a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP Pop a Word from the Stack</a><br>
<a href="POPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPA.HTM">POPA/POPAD Pop all General Registers</a><br>
<a href="POPF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPF.HTM">POPF/POPFD Pop Stack into FLAGS or EFLAGS Register</a><br>
<a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH Push Operand onto the Stack</a><br>
<a href="PUSHA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHA.HTM">PUSHA/PUSHAD Push all General Registers</a><br>
<a href="PUSHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHF.HTM">PUSHF/PUSHFD Push Flags Register onto the Stack</a><br>
<a href="RCL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RCL.HTM">RCL/RCR/ROL/ROR Rotate</a><br>
<a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REP/REPE/REPZ/REPNE/REPNZ Repeat Following String Operation</a><br>
<a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET Return from Procedure</a><br>
<a href="SAHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAHF.HTM">SAHF Store AH into Flags</a><br>
<a href="SAL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SAL.HTM">SAL/SAR/SHL/SHR Shift Instructions</a><br>
<a href="SBB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SBB.HTM">SBB Integer Subtraction with Borrow</a><br>
<a href="SCAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SCAS.HTM">SCAS/SCASB/SCASW/SCASD Compare String Data</a><br>
<a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETcc Byte Set on Condition</a><br>
<a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SGDT/SIDT Store Global/Interrupt Descriptor Table Register</a><br>
<a href="SHLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SHLD.HTM">SHLD Double Precision Shift Left</a><br>
<a href="SHRD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SHRD.HTM">SHRD Double Precision Shift Right</a><br>
<a href="SLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SLDT.HTM">SLDT Store Local Descriptor Table Register</a><br>
<a href="SMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SMSW.HTM">SMSW Store Machine Status Word</a><br>
<a href="STC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STC.HTM">STC Set Carry Flag</a><br>
<a href="STD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STD.HTM">STD Set Direction Flag</a><br>
<a href="STI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STI.HTM">STI Set Interrupt Flag</a><br>
<a href="STOS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STOS.HTM">STOS/STOSB/STOSW/STOSD Store String Data</a><br>
<a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR Store Task Register</a><br>
<a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB Integer Subtraction</a><br>
<a href="TEST.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TEST.HTM">TEST Logical Compare</a><br>
<a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERR, VERW Verify a Segment for Reading or Writing</a><br>
<a href="WAIT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/WAIT.HTM">WAIT Wait until BUSY# Pin is Inactive (HIGH)</a><br>
<a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG Exchange Register/Memory with Register</a><br>
<a href="XLAT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XLAT.HTM">XLAT/XLATB Table Look-up Translation</a><br>
<a href="XOR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XOR.HTM">XOR Logical Exclusive OR</a>
<p>
<hr>
<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
<b>prev:</b> <a href="S16_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_04.HTM">16.4 Transferring Control Among Mixed Code Segments&gt;</a><br>
<b>next:</b> <a href="S17_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_01.HTM">17.1 Operand-Size and Address-Size Attributes</a>
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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CALL</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a><br>
<b>next:</b><a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM"> CBW/CWDE Convert Byte to Word/Convert Word to Doubleword</a>
<p>
<hr>
<p>
<h1>CALL -- Call Procedure</h1>
<pre>
Opcode Instruction Clocks
Values of ts are given by the following table:
New Task
386 TSS 386 TSS 286 TSS
Old VM = 0 VM = 1
Task Via Task Gate?
N Y N Y N Y
386 300 309 217 226 273 282
TSS VM=0
286 298 307 217 226 273 282
TSS Description
E8 cw CALL rel16 7+m Call near, displacement relative
to next instruction
FF /2 CALL r/m16 7+m/10+m Call near, register
indirect/memory indirect
9A cd CALL ptr16:16 17+m,pm=34+m Call intersegment, to full
pointer given
9A cd CALL ptr16:16 pm=52+m Call gate, same privilege
9A cd CALL ptr16:16 pm=86+m Call gate, more privilege, no
parameters
9A cd CALL ptr16:16 pm=94+4x+m Call gate, more privilege, x
parameters
9A cd CALL ptr16:16 ts Call to task
FF /3 CALL m16:16 22+m,pm=38+m Call intersegment, address at
r/m dword
FF /3 CALL m16:16 pm=56+m Call gate, same privilege
FF /3 CALL m16:16 pm=90+m Call gate, more privilege, no
parameters
FF /3 CALL m16:16 pm=98+4x+m Call gate, more privilege, x
parameters
FF /3 CALL m16:16 5 + ts Call to task
E8 cd CALL rel32 7+m Call near, displacement relative
to next instruction
FF /2 CALL r/m32 7+m/10+m Call near, indirect
9A cp CALL ptr16:32 17+m,pm=34+m Call intersegment, to full
pointer given
9A cp CALL ptr16:32 pm=52+m Call gate, same privilege
9A cp CALL ptr16:32 pm=86+m Call gate, more privilege, no
parameters
9A cp CALL ptr32:32 pm=94+4x+m Call gate, more privilege, x
parameters
9A cp CALL ptr16:32 ts Call to task
FF /3 CALL m16:32 22+m,pm=38+m Call intersegment, address at
r/m dword
FF /3 CALL m16:32 pm=56+m Call gate, same privilege
FF /3 CALL m16:32 pm=90+m Call gate, more privilege, no
parameters
FF /3 CALL m16:32 pm=98+4x+m Call gate, more privilege, x
parameters
FF /3 CALL m16:32 5 + ts Call to task
</pre>
<em>
<h3>Note</h3>
Values of ts are given by the following table:
<pre>
New Task
386 TSS 386 TSS 286 TSS
Old VM = 0 VM = 1
Task Via Task Gate?
N Y N Y N Y
386 300 309 217 226 273 282
TSS VM=0
286 298 307 217 226 273 282
TSS
</pre>
</em>
<h2>Operation</h2>
<pre>
IF rel16 or rel32 type of call
THEN (* near relative call *)
IF OperandSize = 16
THEN
Push(IP);
EIP := (EIP + rel16) AND 0000FFFFH;
ELSE (* OperandSize = 32 *)
Push(EIP);
EIP := EIP + rel32;
FI;
FI;
IF r/m16 or r/m32 type of call
THEN (* near absolute call *)
IF OperandSize = 16
THEN
Push(IP);
EIP := [r/m16] AND 0000FFFFH;
ELSE (* OperandSize = 32 *)
Push(EIP);
EIP := [r/m32];
FI;
FI;
IF (PE = 0 OR (PE = 1 AND VM = 1))
(* real mode or virtual 8086 mode *)
AND instruction = far CALL
(* i.e., operand type is m16:16, m16:32, ptr16:16, ptr16:32 *)
THEN
IF OperandSize = 16
THEN
Push(CS);
Push(IP); (* address of next instruction; 16 bits *)
ELSE
Push(CS); (* padded with 16 high-order bits *)
Push(EIP); (* address of next instruction; 32 bits *)
FI;
IF operand type is m16:16 or m16:32
THEN (* indirect far call *)
IF OperandSize = 16
THEN
CS:IP := [m16:16];
EIP := EIP AND 0000FFFFH; (* clear upper 16 bits *)
ELSE (* OperandSize = 32 *)
CS:EIP := [m16:32];
FI;
FI;
IF operand type is ptr16:16 or ptr16:32
THEN (* direct far call *)
IF OperandSize = 16
THEN
CS:IP := ptr16:16;
EIP := EIP AND 0000FFFFH; (* clear upper 16 bits *)
ELSE (* OperandSize = 32 *)
CS:EIP := ptr16:32;
FI;
FI;
FI;
IF (PE = 1 AND VM = 0) (* Protected mode, not V86 mode *)
AND instruction = far CALL
THEN
If indirect, then check access of EA doubleword;
#GP(0) if limit violation;
New CS selector must not be null else #GP(0);
Check that new CS selector index is within its
descriptor table limits; else #GP(new CS selector);
Examine AR byte of selected descriptor for various legal values;
depending on value:
go to CONFORMING-CODE-SEGMENT;
go to NONCONFORMING-CODE-SEGMENT;
go to CALL-GATE;
go to TASK-GATE;
go to TASK-STATE-SEGMENT;
ELSE #GP(code segment selector);
FI;
CONFORMING-CODE-SEGMENT:
DPL must be &lt;= CPL ELSE #GP(code segment selector);
Segment must be present ELSE #NP(code segment selector);
Stack must be big enough for return address ELSE #SS(0);
Instruction pointer must be in code segment limit ELSE #GP(0);
Load code segment descriptor into CS register;
Load CS with new code segment selector;
Load EIP with zero-extend(new offset);
IF OperandSize=16 THEN EIP := EIP AND 0000FFFFH; FI;
NONCONFORMING-CODE-SEGMENT:
RPL must be &lt;= CPL ELSE #GP(code segment selector)
DPL must be = CPL ELSE #GP(code segment selector)
Segment must be present ELSE #NP(code segment selector)
Stack must be big enough for return address ELSE #SS(0)
Instruction pointer must be in code segment limit ELSE #GP(0)
Load code segment descriptor into CS register
Load CS with new code segment selector
Set RPL of CS to CPL
Load EIP with zero-extend(new offset);
IF OperandSize=16 THEN EIP := EIP AND 0000FFFFH; FI;
CALL-GATE:
Call gate DPL must be &gt;= CPL ELSE #GP(call gate selector)
Call gate DPL must be &gt;= RPL ELSE #GP(call gate selector)
Call gate must be present ELSE #NP(call gate selector)
Examine code segment selector in call gate descriptor:
Selector must not be null ELSE #GP(0)
Selector must be within its descriptor table
limits ELSE #GP(code segment selector)
AR byte of selected descriptor must indicate code
segment ELSE #GP(code segment selector)
DPL of selected descriptor must be &lt;= CPL ELSE
#GP(code segment selector)
IF non-conforming code segment AND DPL &lt; CPL
THEN go to MORE-PRIVILEGE
ELSE go to SAME-PRIVILEGE
FI;
MORE-PRIVILEGE:
Get new SS selector for new privilege level from TSS
Check selector and descriptor for new SS:
Selector must not be null ELSE #TS(0)
Selector index must be within its descriptor
table limits ELSE #TS(SS selector)
Selector's RPL must equal DPL of code segment
ELSE #TS(SS selector)
Stack segment DPL must equal DPL of code
segment ELSE #TS(SS selector)
Descriptor must indicate writable data segment
ELSE #TS(SS selector)
Segment present ELSE #SS(SS selector)
IF OperandSize=32
THEN
New stack must have room for parameters plus 16 bytes
ELSE #SS(0)
EIP must be in code segment limit ELSE #GP(0)
Load new SS:eSP value from TSS
Load new CS:EIP value from gate
ELSE
New stack must have room for parameters plus 8 bytes ELSE #SS(0)
IP must be in code segment limit ELSE #GP(0)
Load new SS:eSP value from TSS
Load new CS:IP value from gate
FI;
Load CS descriptor
Load SS descriptor
Push long pointer of old stack onto new stack
Get word count from call gate, mask to 5 bits
Copy parameters from old stack onto new stack
Push return address onto new stack
Set CPL to stack segment DPL
Set RPL of CS to CPL
SAME-PRIVILEGE:
IF OperandSize=32
THEN
Stack must have room for 6-byte return address (padded to 8 bytes)
ELSE #SS(0)
EIP must be within code segment limit ELSE #GP(0)
Load CS:EIP from gate
ELSE
Stack must have room for 4-byte return address ELSE #SS(0)
IP must be within code segment limit ELSE #GP(0)
Load CS:IP from gate
FI;
Push return address onto stack
Load code segment descriptor into CS register
Set RPL of CS to CPL
TASK-GATE:
Task gate DPL must be &gt;= CPL ELSE #TS(gate selector)
Task gate DPL must be &gt;= RPL ELSE #TS(gate selector)
Task Gate must be present ELSE #NP(gate selector)
Examine selector to TSS, given in Task Gate descriptor:
Must specify global in the local/global bit ELSE #TS(TSS selector)
Index must be within GDT limits ELSE #TS(TSS selector)
TSS descriptor AR byte must specify nonbusy TSS
ELSE #TS(TSS selector)
Task State Segment must be present ELSE #NP(TSS selector)
SWITCH-TASKS (with nesting) to TSS
IP must be in code segment limit ELSE #TS(0)
TASK-STATE-SEGMENT:
TSS DPL must be &gt;= CPL else #TS(TSS selector)
TSS DPL must be &gt;= RPL ELSE #TS(TSS selector)
TSS descriptor AR byte must specify available TSS
ELSE #TS(TSS selector)
Task State Segment must be present ELSE #NP(TSS selector)
SWITCH-TASKS (with nesting) to TSS
IP must be in code segment limit ELSE #TS(0)
</pre>
<h2>Description</h2>
The CALL instruction causes the procedure named in the operand to be executed. When the procedure is complete (a return instruction is executed within the procedure), execution continues at the instruction that follows the CALL instruction.
<p>The action of the different forms of the instruction are described below.
<p><strong>Near calls</strong> are those with destinations of type r/m16, r/m32, rel16, rel32; changing or saving the segment register value is not necessary. The CALL rel16 and CALL rel32 forms add a signed offset to the address of the instruction following CALL to determine the destination. The rel16 form is used when the instruction's operand-size attribute is 16 bits; rel32 is used when the operand-size attribute is 32 bits. The result is stored in the 32-bit EIP register. With rel16, the upper 16 bits of EIP are cleared, resulting in an offset whose value does not exceed 16 bits. CALL r/m16 and CALL r/m32 specify a register or memory location from which the absolute segment offset is fetched. The offset fetched from r/m is 32 bits for an operand-size attribute of 32 (r/m32), or 16 bits for an operand-size of 16 (r/m16). The offset of the instruction following CALL is pushed onto the stack. It will be popped by a near <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> instruction within the procedure. The CS register is not changed by this form of CALL.
<p>The <strong>far calls</strong>, CALL ptr16:16 and CALL ptr16:32, use a four-byte or six-byte operand as a long pointer to the procedure called. The CALL m16:16 and m16:32 forms fetch the long pointer from the memory location specified (indirection). In Real Address Mode or Virtual 8086 Mode, the long pointer provides 16 bits for the CS register and 16 or 32 bits for the EIP register (depending on the operand-size attribute). These forms of the instruction push both CS and IP or EIP as a return address.
<p>In Protected Mode, both long pointer forms consult the AR byte in the descriptor indexed by the selector part of the long pointer. Depending on the value of the AR byte, the call will perform one of the following types of control transfers:
<ul>
<li>A far call to the same protection level
<li>An inter-protection level far call
<li>A task switch
</ul>
For more information on Protected Mode control transfers, refer to <a href="C06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C06.HTM">Chapter 6</a> and <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7</a>.
<h2>Flags Affected</h2>
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur
<h2>Protected Mode Exceptions</h2>
For <strong>far calls</strong>: #GP, #NP, #SS, and #TS, as indicated in the list above
<p>For <strong>near direct calls</strong>: #GP(0) if procedure location is beyond the code segment limits; #SS(0) if pushing the return address exceeds the bounds of the stack segment; #PF (fault-code) for a page fault For a <strong>near indirect call</strong>: #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #GP(0) if the indirect offset obtained is beyond the code segment limits; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<h2>Notes</h2>
Any far call from a 32-bit code segment to 16-bit code segments should be made from the first 64K bytes of the 32-bit code segment, since the operand-size attribute of the instruction is set to 16, thus allowing only a 16-bit return address offset to be saved.
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a><br>
<b>next:</b><a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM"> CBW/CWDE Convert Byte to Word/Convert Word to Doubleword</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CBW</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM"> CALL Call Procedure</a><br>
<b>next:</b><a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM"> CLC Clear Carry Flag</a>
<p>
<hr>
<p>
<h1>CBW/CWDE -- Convert Byte to Word/Convert Word to Doubleword</h1>
<pre>
Opcode Instruction Clocks Description
98 CBW 3 AX := sign-extend of AL
98 CWDE 3 EAX := sign-extend of AX
</pre>
<h2>Operation</h2>
<pre>
IF OperandSize = 16 (* instruction = CBW *)
THEN AX := SignExtend(AL);
ELSE (* OperandSize = 32, instruction = CWDE *)
EAX := SignExtend(AX);
FI;
</pre>
<h2>Description</h2>
CBW converts the signed byte in AL to a signed word in AX by extending the most significant bit of AL (the sign bit) into all of the bits of AH. CWDE converts the signed word in AX to a doubleword in EAX by extending the most significant bit of AX into the two most significant bytes of EAX. Note that CWDE is different from CWD. CWD uses DX:AX rather than EAX as a destination.
<h2>Flags Affected</h2>
None
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM"> CALL Call Procedure</a><br>
<b>next:</b><a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM"> CLC Clear Carry Flag</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CLC</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM"> CBW/CWDE Convert Byte to Word/Convert Word to Doubleword</a><br>
<b>next:</b><a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM"> CLD Clear Direction Flag</a>
<p>
<hr>
<p>
<h1>CLC -- Clear Carry Flag</h1>
<pre>
Opcode Instruction Clocks Description
F8 CLC 2 Clear carry flag
</pre>
<h2>Operation</h2>
<pre>
CF := 0;
</pre>
<h2>Description</h2>
CLC sets the carry flag to zero. It does not affect other flags or registers.
<h2>Flags Affected</h2>
CF := 0
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CBW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CBW.HTM"> CBW/CWDE Convert Byte to Word/Convert Word to Doubleword</a><br>
<b>next:</b><a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM"> CLD Clear Direction Flag</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CLD</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM"> CLC Clear Carry Flag</a><br>
<b>next:</b><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM"> CLI Clear Interrupt Flag</a>
<p>
<hr>
<p>
<h1>CLD -- Clear Direction Flag</h1>
<pre>
Opcode Instruction Clocks Description
FC CLD 2 Clear direction flag; SI and DI
will increment during string
instructions
</pre>
<h2>Operation</h2>
<pre>
DF := 0;
</pre>
<h2>Description</h2>
CLD clears the direction flag. No other flags or registers are affected. After CLD is executed, string operations will increment the index registers (SI and/or DI) that they use.
<h2>Flags Affected</h2>
DF := 0
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLC.HTM"> CLC Clear Carry Flag</a><br>
<b>next:</b><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM"> CLI Clear Interrupt Flag</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CLI</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM"> CLD Clear Direction Flag</a><br>
<b>next:</b><a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM"> CLTS Clear Task-Switched Flag in CR0</a>
<p>
<hr>
<p>
<h1>CLI -- Clear Interrupt Flag</h1>
<pre>
Opcode Instruction Clocks Description
FA CLI 3 Clear interrupt flag; interrupts disabled
</pre>
<h2>Operation</h2>
<pre>
IF := 0;
</pre>
<h2>Description</h2>
CLI clears the interrupt flag if the current privilege level is at least as privileged as IOPL. No other flags are affected. External interrupts are not recognized at the end of the CLI instruction or from that point on until the interrupt flag is set.
<h2>Flags Affected</h2>
IF := 0
<h2>Protected Mode Exceptions</h2>
#GP(0) if the current privilege level is greater (has less privilege) than the IOPL in the flags register. IOPL specifies the least privileged level at which I/O can be performed.
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
#GP(0) as for Protected Mode
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM"> CLD Clear Direction Flag</a><br>
<b>next:</b><a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM"> CLTS Clear Task-Switched Flag in CR0</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CLTS</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM"> CLI Clear Interrupt Flag</a><br>
<b>next:</b><a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM"> CMC Complement Carry Flag</a>
<p>
<hr>
<p>
<h1>CLTS -- Clear Task-Switched Flag in CR0</h1>
<pre>
Opcode Instruction Clocks Description
OF 06 CLTS 5 Clear task-switched flag
</pre>
<h2>Operation</h2>
<pre>
TS Flag in CR0 := 0;
</pre>
<h2>Description</h2>
CLTS clears the task-switched (TS) flag in register CR0. This flag is set by the 80386 every time a task switch occurs. The TS flag is used to manage processor extensions as follows:
<ul>
<li>Every execution of an ESC instruction is trapped if the TS flag is set.
<li>Execution of a WAIT instruction is trapped if the MP flag and the TS flag are both set.
</ul>
Thus, if a task switch was made after an ESC instruction was begun, the processor extension's context may need to be saved before a new ESC instruction can be issued. The fault handler saves the context and resets the TS flag.
<p>CLTS appears in operating system software, not in application programs. It is a privileged instruction that can only be executed at privilege level 0.
<h2>Flags Affected</h2>
TS := 0 (TS is in CR0, not the flag register)
<h2>Protected Mode Exceptions</h2>
#GP(0) if CLTS is executed with a current privilege level other than 0
<h2>Real Address Mode Exceptions</h2>
None (valid in Real Address Mode to allow initialization for Protected Mode)
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM"> CLI Clear Interrupt Flag</a><br>
<b>next:</b><a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM"> CMC Complement Carry Flag</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CMC</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM"> CLTS Clear Task-Switched Flag in CR0</a><br>
<b>next:</b><a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM"> CMP Compare Two Operands</a>
<p>
<hr>
<p>
<h1>CMC -- Complement Carry Flag</h1>
<pre>
Opcode Instruction Clocks Description
F5 CMC 2 Complement carry flag
</pre>
<h2>Operation</h2>
<pre>
CF := NOT CF;
</pre>
<h2>Description</h2>
CMC reverses the setting of the carry flag. No other flags are affected.
<h2>Flags Affected</h2>
CF as described above
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM"> CLTS Clear Task-Switched Flag in CR0</a><br>
<b>next:</b><a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM"> CMP Compare Two Operands</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CMP</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM"> CMC Complement Carry Flag</a><br>
<b>next:</b><a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM"> CMPS/CMPSB/CMPSW/CMPSD Compare String Operands</a>
<p>
<hr>
<p>
<h1>CMP -- Compare Two Operands</h1>
<pre>
Opcode Instruction Clocks Description
3C ib CMP AL,imm8 2 Compare immediate byte to AL
3D iw CMP AX,imm16 2 Compare immediate word to AX
3D id CMP EAX,imm32 2 Compare immediate dword to EAX
80 /7 ib CMP r/m8,imm8 2/5 Compare immediate byte to r/m
byte
81 /7 iw CMP r/m16,imm16 2/5 Compare immediate word to r/m
word
81 /7 id CMP r/m32,imm32 2/5 Compare immediate dword to r/m
dword
83 /7 ib CMP r/m16,imm8 2/5 Compare sign extended immediate
byte to r/m word
83 /7 ib CMP r/m32,imm8 2/5 Compare sign extended immediate
byte to r/m dword
38 /r CMP r/m8,r8 2/5 Compare byte register to r/m
byte
39 /r CMP r/m16,r16 2/5 Compare word register to r/m
word
39 /r CMP r/m32,r32 2/5 Compare dword register to r/m
dword
3A /r CMP r8,r/m8 2/6 Compare r/m byte to byte
register
3B /r CMP r16,r/m16 2/6 Compare r/m word to word
register
3B /r CMP r32,r/m32 2/6 Compare r/m dword to dword
register
</pre>
<h2>Operation</h2>
<pre>
LeftSRC - SignExtend(RightSRC);
(* CMP does not store a result; its purpose is to set the flags *)
</pre>
<h2>Description</h2>
CMP subtracts the second operand from the first but, unlike the <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> instruction, does not store the result; only the flags are changed. CMP is typically used in conjunction with conditional jumps and the <a href="SETCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SETCC.HTM">SETcc</a> instruction. (Refer to Appendix D for the list of signed and unsigned flag tests provided.) If an operand greater than one byte is compared to an immediate byte, the byte value is first sign-extended.
<h2>Flags Affected</h2>
OF, SF, ZF, AF, PF, and CF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>
<h2>Protected Mode Exceptions</h2>
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMC.HTM"> CMC Complement Carry Flag</a><br>
<b>next:</b><a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM"> CMPS/CMPSB/CMPSW/CMPSD Compare String Operands</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CMPS</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM"> CMP Compare Two Operands</a><br>
<b>next:</b><a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM"> CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword</a>
<p>
<hr>
<p>
<h1>CMPS/CMPSB/CMPSW/CMPSD -- Compare String Operands</h1>
<pre>
Opcode Instruction Clocks Description
A6 CMPS m8,m8 10 Compare bytes ES:[(E)DI] (second
operand) with [(E)SI] (first
operand)
A7 CMPS m16,m16 10 Compare words ES:[(E)DI] (second
operand) with [(E)SI] (first
operand)
A7 CMPS m32,m32 10 Compare dwords ES:[(E)DI]
(second operand) with [(E)SI]
(first operand)
A6 CMPSB 10 Compare bytes ES:[(E)DI] with
DS:[SI]
A7 CMPSW 10 Compare words ES:[(E)DI] with
DS:[SI]
A7 CMPSD 10 Compare dwords ES:[(E)DI] with
DS:[SI]
</pre>
<h2>Operation</h2>
<pre>
IF (instruction = CMPSD) OR
(instruction has operands of type DWORD)
THEN OperandSize := 32;
ELSE OperandSize := 16;
FI;
IF AddressSize = 16
THEN
use SI for source-index and DI for destination-index
ELSE (* AddressSize = 32 *)
use ESI for source-index and EDI for destination-index;
FI;
IF byte type of instruction
THEN
[source-index] - [destination-index]; (* byte comparison *)
IF DF = 0 THEN IncDec := 1 ELSE IncDec := -1; FI;
ELSE
IF OperandSize = 16
THEN
[source-index] - [destination-index]; (* word comparison *)
IF DF = 0 THEN IncDec := 2 ELSE IncDec := -2; FI;
ELSE (* OperandSize = 32 *)
[source-index] - [destination-index]; (* dword comparison *)
IF DF = 0 THEN IncDec := 4 ELSE IncDec := -4; FI;
FI;
FI;
source-index := source-index + IncDec;
destination-index := destination-index + IncDec;
</pre>
<h2>Description</h2>
CMPS compares the byte, word, or doubleword pointed to by the source-index register with the byte, word, or doubleword pointed to by the destination-index register.
<p>If the address-size attribute of this instruction is 16 bits, SI and DI will be used for source- and destination-index registers; otherwise ESI and EDI will be used. Load the correct index values into SI and DI (or ESI and EDI) before executing CMPS.
<p>The comparison is done by subtracting the operand indexed by the destination-index register from the operand indexed by the source-index register.
<p>Note that the direction of subtraction for CMPS is [SI] - [DI] or [ESI] - [EDI]. The left operand (SI or ESI) is the source and the right operand (DI or EDI) is the destination. This is the reverse of the usual Intel convention in which the left operand is the destination and the right operand is the source.
<p>The result of the subtraction is not stored; only the flags reflect the change. The types of the operands determine whether bytes, words, or doublewords are compared. For the first operand (SI or ESI), the DS register is used, unless a segment override byte is present. The second operand (DI or EDI) must be addressable from the ES register; no segment override is possible.
<p>After the comparison is made, both the source-index register and destination-index register are automatically advanced. If the direction flag is 0 (<a href="CLD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLD.HTM">CLD</a> was executed), the registers increment; if the direction flag is 1 (<a href="STD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STD.HTM">STD</a> was executed), the registers decrement. The registers increment or decrement by 1 if a byte is compared, by 2 if a word is compared, or by 4 if a doubleword is compared.
<p>CMPSB, CMPSW and CMPSD are synonyms for the byte, word, and doubleword CMPS instructions, respectively.
<p>CMPS can be preceded by the <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REPE</a> or <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REPNE</a> prefix for block comparison of CX or ECX bytes, words, or doublewords. Refer to the description of the <a href="REP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/REP.HTM">REP</a> instruction for more information on this operation.
<h2>Flags Affected</h2>
OF, SF, ZF, AF, PF, and CF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>
<h2>Protected Mode Exceptions</h2>
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF (fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMP.HTM"> CMP Compare Two Operands</a><br>
<b>next:</b><a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM"> CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword</a>
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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode CWD</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM"> CMPS/CMPSB/CMPSW/CMPSD Compare String Operands</a><br>
<b>next:</b><a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM"> DAA Decimal Adjust AL after Addition</a>
<p>
<hr>
<p>
<h1>CWD/CDQ -- Convert Word to Doubleword/Convert Doubleword to Quadword</h1>
<pre>
Opcode Instruction Clocks Description
99 CWD 2 DX:AX := sign-extend of AX
99 CDQ 2 EDX:EAX := sign-extend of EAX
</pre>
<h2>Operation</h2>
<pre>
IF OperandSize = 16 (* CWD instruction *)
THEN
IF AX &lt; 0 THEN DX := 0FFFFH; ELSE DX := 0; FI;
ELSE (* OperandSize = 32, CDQ instruction *)
IF EAX &lt; 0 THEN EDX := 0FFFFFFFFH; ELSE EDX := 0; FI;
FI;
</pre>
<h2>Description</h2>
CWD converts the signed word in AX to a signed doubleword in DX:AX by extending the most significant bit of AX into all the bits of DX. CDQ converts the signed doubleword in EAX to a signed 64-bit integer in the register pair EDX:EAX by extending the most significant bit of EAX (the sign bit) into all the bits of EDX. Note that CWD is different from CWDE. CWDE uses EAX as a destination, instead of DX:AX.
<h2>Flags Affected</h2>
None
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CMPS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CMPS.HTM"> CMPS/CMPSB/CMPSW/CMPSD Compare String Operands</a><br>
<b>next:</b><a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM"> DAA Decimal Adjust AL after Addition</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode DAA</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM"> CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword</a><br>
<b>next:</b><a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM"> DAS Decimal Adjust AL after Subtraction</a>
<p>
<hr>
<p>
<h1>DAA -- Decimal Adjust AL after Addition</h1>
<pre>
Opcode Instruction Clocks Description
27 DAA 4 Decimal adjust AL after addition
</pre>
<h2>Operation</h2>
<pre>
IF ((AL AND 0FH) &gt; 9) OR (AF = 1)
THEN
AL := AL + 6;
AF := 1;
ELSE
AF := 0;
FI;
IF (AL &gt; 9FH) OR (CF = 1)
THEN
AL := AL + 60H;
CF := 1;
ELSE CF := 0;
FI;
</pre>
<h2>Description</h2>
Execute DAA only after executing an <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> instruction that leaves a two-BCD-digit byte result in the AL register. The <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a> operands should consist of two packed BCD digits. The DAA instruction adjusts AL to contain the correct two-digit packed decimal result.
<h2>Flags Affected</h2>
AF and CF as described above; SF, ZF, PF, and CF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>.
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="CWD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CWD.HTM"> CWD/CDQ Convert Word to Doubleword/Convert Doubleword to Quadword</a><br>
<b>next:</b><a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM"> DAS Decimal Adjust AL after Subtraction</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode DAS</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM"> DAA Decimal Adjust AL after Addition</a><br>
<b>next:</b><a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM"> DEC Decrement by 1</a>
<p>
<hr>
<p>
<h1>DAS -- Decimal Adjust AL after Subtraction</h1>
<pre>
Opcode Instruction Clocks Description
2F DAS 4 Decimal adjust AL after subtraction
</pre>
<h2>Operation</h2>
<pre>
IF (AL AND 0FH) &gt; 9 OR AF = 1
THEN
AL := AL - 6;
AF := 1;
ELSE
AF := 0;
FI;
IF (AL &gt; 9FH) OR (CF = 1)
THEN
AL := AL - 60H;
CF := 1;
ELSE CF := 0;
FI;
</pre>
<h2>Description</h2>
Execute DAS only after a subtraction instruction that leaves a two-BCD-digit byte result in the AL register. The operands should consist of two packed BCD digits. DAS adjusts AL to contain the correct packed two-digit decimal result.
<h2>Flags Affected</h2>
AF and CF as described above; SF, ZF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>.
<h2>Protected Mode Exceptions</h2>
None
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DAA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAA.HTM"> DAA Decimal Adjust AL after Addition</a><br>
<b>next:</b><a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM"> DEC Decrement by 1</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode DEC</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM"> DAS Decimal Adjust AL after Subtraction</a><br>
<b>next:</b><a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM"> DIV Unsigned Divide</a>
<p>
<hr>
<p>
<h1>DEC -- Decrement by 1</h1>
<pre>
Opcode Instruction Clocks Description
FE /1 DEC r/m8 2/6 Decrement r/m byte by 1
FF /1 DEC r/m16 2/6 Decrement r/m word by 1
DEC r/m32 2/6 Decrement r/m dword by 1
48+rw DEC r16 2 Decrement word register by 1
48+rw DEC r32 2 Decrement dword register by 1
</pre>
<h2>Operation</h2>
<pre>
DEST := DEST - 1;
</pre>
<h2>Description</h2>
DEC subtracts 1 from the operand. DEC does not change the carry flag. To affect the carry flag, use the <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a> instruction with an immediate operand of 1.
<h2>Flags Affected</h2>
OF, SF, ZF, AF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>.
<h2>Protected Mode Exceptions</h2>
#GP(0) if the result is a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DAS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DAS.HTM"> DAS Decimal Adjust AL after Subtraction</a><br>
<b>next:</b><a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM"> DIV Unsigned Divide</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode DIV</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM"> DEC Decrement by 1</a><br>
<b>next:</b><a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM"> ENTER Make Stack Frame for Procedure Parameters</a>
<p>
<hr>
<p>
<h1>DIV -- Unsigned Divide</h1>
<pre>
Opcode Instruction Clocks Description
F6 /6 DIV AL,r/m8 14/17 Unsigned divide AX by r/m byte
(AL=Quo, AH=Rem)
F7 /6 DIV AX,r/m16 22/25 Unsigned divide DX:AX by r/m
word (AX=Quo, DX=Rem)
F7 /6 DIV EAX,r/m32 38/41 Unsigned divide EDX:EAX by r/m
dword (EAX=Quo, EDX=Rem)
</pre>
<h2>Operation</h2>
<pre>
temp := dividend / divisor;
IF temp does not fit in quotient
THEN Interrupt 0;
ELSE
quotient := temp;
remainder := dividend MOD (r/m);
FI;
</pre>
<em>
<h3>Note</h3>
Divisions are unsigned. The divisor is given by the r/m operand. The dividend, quotient, and remainder use implicit registers. Refer to the table under &quot;Description&quot; </em>
<h2>Description</h2>
DIV performs an unsigned division. The dividend is implicit; only the divisor is given as an operand. The remainder is always less than the divisor. The type of the divisor determines which registers to use as follows:
<pre>
Size Dividend Divisor Quotient Remainder
byte AX r/m8 AL AH
word DX:AX r/m16 AX DX
dword EDX:EAX r/m32 EAX EDX
</pre>
<h2>Flags Affected</h2>
OF, SF, ZF, AR, PF, CF are undefined.
<h2>Protected Mode Exceptions</h2>
Interrupt 0 if the quotient is too large to fit in the designated register (AL, AX, or EAX), or if the divisor is 0; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
Interrupt 0 if the quotient is too big to fit in the designated register (AL, AX, or EAX), or if the divisor is 0; Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
<h2>Virtual 8086 Mode Exceptions</h2>
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM"> DEC Decrement by 1</a><br>
<b>next:</b><a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM"> ENTER Make Stack Frame for Procedure Parameters</a>
</body>

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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
<html>
<head>
<title>80386 Programmer's Reference Manual -- Opcode ENTER</title>
</head>
<body>
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM"> DIV Unsigned Divide</a><br>
<b>next:</b><a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM"> HLT Halt</a>
<p>
<hr>
<p>
<h1>ENTER -- Make Stack Frame for Procedure Parameters</h1>
<pre>
Opcode Instruction Clocks Description
C8 iw 00 ENTER imm16,0 10 Make procedure stack frame
C8 iw 01 ENTER imm16,1 12 Make stack frame for procedure
parameters
C8 iw ib ENTER imm16,imm8 15+4(n-1) Make stack frame for
procedure parameters
</pre>
<h2>Operation</h2>
<pre>
level := level MOD 32
IF OperandSize = 16 THEN Push(BP) ELSE Push (EBP) FI;
(* Save stack pointer *)
frame-ptr := eSP
IF level &gt; 0
THEN (* level is rightmost parameter *)
FOR i := 1 TO level - 1
DO
IF OperandSize = 16
THEN
BP := BP - 2;
Push[BP]
ELSE (* OperandSize = 32 *)
EBP := EBP - 4;
Push[EBP];
FI;
OD;
Push(frame-ptr)
FI;
IF OperandSize = 16 THEN BP := frame-ptr ELSE EBP := frame-ptr; FI;
IF StackAddrSize = 16
THEN SP := SP - First operand;
ELSE ESP := ESP - ZeroExtend(First operand);
FI;
</pre>
<h2>Description</h2>
ENTER creates the stack frame required by most block-structured high-level languages. The first operand specifies the number of bytes of dynamic storage allocated on the stack for the routine being entered. The second operand gives the lexical nesting level (0 to 31) of the routine within the high-level language source code. It determines the number of stack frame pointers copied into the new stack frame from the preceding frame. BP (or EBP, if the operand-size attribute is 32 bits) is the current stack frame pointer.
<p>If the operand-size attribute is 16 bits, the processor uses BP as the frame pointer and SP as the stack pointer. If the operand-size attribute is 32 bits, the processor uses EBP for the frame pointer and ESP for the stack pointer.
<p>If the second operand is 0, ENTER pushes the frame pointer (BP or EBP) onto the stack; ENTER then subtracts the first operand from the stack pointer and sets the frame pointer to the current stack-pointer value.
<p>For example, a procedure with 12 bytes of local variables would have an ENTER 12,0 instruction at its entry point and a <a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM">LEAVE</a> instruction before every <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a>. The 12 local bytes would be addressed as negative offsets from the frame pointer.
<h2>Flags Affected</h2>
None
<h2>Protected Mode Exceptions</h2>
#SS(0) if SP or ESP would exceed the stack limit at any point during instruction execution; #PF(fault-code) for a page fault
<h2>Real Address Mode Exceptions</h2>
None
<h2>Virtual 8086 Mode Exceptions</h2>
None
<p>
<hr>
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
<b>prev:</b><a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM"> DIV Unsigned Divide</a><br>
<b>next:</b><a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM"> HLT Halt</a>
</body>

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