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study/Ref-docs/manual Intel386/I386Manual/MOV.HTM
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study/Ref-docs/manual Intel386/I386Manual/MOV.HTM
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<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<html>
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<head>
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<title>80386 Programmer's Reference Manual -- Opcode MOV</title>
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</head>
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<body>
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<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM"> LTR Load Task Register</a><br>
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<b>next:</b><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM"> MOV Move to/from Special Registers</a>
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<p>
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<hr>
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<p>
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<h1>MOV -- Move Data</h1>
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<pre>
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Opcode Instruction Clocks Description
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88 /r MOV r/m8,r8 2/2 Move byte register to r/m byte
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89 /r MOV r/m16,r16 2/2 Move word register to r/m word
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89 /r MOV r/m32,r32 2/2 Move dword register to r/m dword
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8A /r MOV r8,r/m8 2/4 Move r/m byte to byte register
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8B /r MOV r16,r/m16 2/4 Move r/m word to word register
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8B /r MOV r32,r/m32 2/4 Move r/m dword to dword register
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8C /r MOV r/m16,Sreg 2/2 Move segment register to r/m word
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8D /r MOV Sreg,r/m16 2/5,pm=18/19 Move r/m word to segment register
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A0 MOV AL,moffs8 4 Move byte at (seg:offset) to AL
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A1 MOV AX,moffs16 4 Move word at (seg:offset) to AX
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A1 MOV EAX,moffs32 4 Move dword at (seg:offset) to EAX
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A2 MOV moffs8,AL 2 Move AL to (seg:offset)
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A3 MOV moffs16,AX 2 Move AX to (seg:offset)
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A3 MOV moffs32,EAX 2 Move EAX to (seg:offset)
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B0 + rb MOV reg8,imm8 2 Move immediate byte to register
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B8 + rw MOV reg16,imm16 2 Move immediate word to register
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B8 + rd MOV reg32,imm32 2 Move immediate dword to register
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C6 MOV r/m8,imm8 2/2 Move immediate byte to r/m byte
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C7 MOV r/m16,imm16 2/2 Move immediate word to r/m word
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C7 MOV r/m32,imm32 2/2 Move immediate dword to r/m dword
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</pre>
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<em>
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<h3>Notes</h3>
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moffs8, moffs16, and moffs32 all consist of a simple offset relative to the segment base. The 8, 16, and 32 refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16 or 32 bits. </em>
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<h2>Operation</h2>
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<pre>
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DEST := SRC;
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</pre>
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<h2>Description</h2>
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MOV copies the second operand to the first operand.
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<p>If the destination operand is a segment register (DS, ES, SS, etc.), then data from a descriptor is also loaded into the register. The data for the register is obtained from the descriptor table entry for the selector given. A null selector (values 0000-0003) can be loaded into DS and ES registers without causing an exception; however, use of DS or ES causes a #GP(0), and no memory reference occurs.
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<p>A MOV into SS inhibits all interrupts until after the execution of the next instruction (which is presumably a MOV into eSP).
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<p>Loading a segment register under 80386 Protected Mode results in special checks and actions, as described in the following listing:
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<pre>
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IF SS is loaded;
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THEN
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IF selector is null THEN #GP(0);
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FI;
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Selector index must be within its descriptor table limits else
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#GP(selector);
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Selector's RPL must equal CPL else #GP(selector);
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AR byte must indicate a writable data segment else #GP(selector);
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DPL in the AR byte must equal CPL else #GP(selector);
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Segment must be marked present else #SS(selector);
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Load SS with selector;
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Load SS with descriptor.
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FI;
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IF DS, ES, FS or GS is loaded with non-null selector;
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THEN
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Selector index must be within its descriptor table limits
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else #GP(selector);
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AR byte must indicate data or readable code segment else
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#GP(selector);
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IF data or nonconforming code segment
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THEN both the RPL and the CPL must be less than or equal to DPL in
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AR byte;
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ELSE #GP(selector);
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FI;
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Segment must be marked present else #NP(selector);
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Load segment register with selector;
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Load segment register with descriptor;
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FI;
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IF DS, ES, FS or GS is loaded with a null selector;
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THEN
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Load segment register with selector;
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Clear descriptor valid bit;
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FI;
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</pre>
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<h2>Flags Affected</h2>
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None
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<h2>Protected Mode Exceptions</h2>
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#GP, #SS, and #NP if a segment register is being loaded; otherwise, #GP(0) if the destination is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
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<h2>Real Address Mode Exceptions</h2>
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Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
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<h2>Virtual 8086 Mode Exceptions</h2>
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Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
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<p>
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<hr>
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<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM"> LTR Load Task Register</a><br>
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<b>next:</b><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM"> MOV Move to/from Special Registers</a>
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</body>
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