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<title>80386 Programmer's Reference Manual -- Section 9.3</title>
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<b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
<b>prev:</b> <a href="S09_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_02.HTM">9.2 Enabling and Disabling Interrupts</a><br>
<b>next:</b> <a href="S09_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM">9.4 Interrupt Descriptor Table</a>
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<h1>9.3 Priority Among Simultaneous Interrupts and Exceptions</h1>
If more than one interrupt or exception is pending at an instruction boundary, the processor services one of them at a time. The priority among classes of interrupt and exception sources is shown in <a href="S09_04.HTM#Table 9-2" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM#Table 9-2">Table 9-2</a>. The processor first services a pending interrupt or exception from the class that has the highest priority, transferring control to the first instruction of the interrupt handler. Lower priority exceptions are discarded; lower priority interrupts are held pending. Discarded exceptions will be rediscovered when the interrupt handler returns control to the point of interruption.
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<p><b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
<b>prev:</b> <a href="S09_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_02.HTM">9.2 Enabling and Disabling Interrupts</a><br>
<b>next:</b> <a href="S09_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM">9.4 Interrupt Descriptor Table</a>
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