165 lines
5.8 KiB
C
165 lines
5.8 KiB
C
/*
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* include/linux/serial.h
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*
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* Copyright (C) 1992 by Theodore Ts'o.
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*
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* Redistribution of this file is permitted under the terms of the GNU
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* Public License (GPL)
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*/
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/*
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* This our internal structure for keeping track of interrupt service
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* routines.
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*/
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typedef struct struct_ISR *async_ISR;
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struct struct_ISR {
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int irq; /* The IRQ assigned for this device */
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int port; /* The base port for this device */
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/* (use is ISR specific) */
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void (*ISR_proc)(async_ISR, int);
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int line; /* The serial line (or base */
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/* serial line) */
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int refcnt; /* How many devices are depending on */
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/* this interrupt (multiport boards) */
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async_ISR next_ISR; /* For the linked list */
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async_ISR prev_ISR;
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};
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/*
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* This is our internal structure for each serial port's state.
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*
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* Many fields are paralleled by the structure used by the serial_struct
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* structure.
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*
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* For definitions of the flags field, see tty.h
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*/
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struct async_struct {
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int baud_base;
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int port;
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async_ISR ISR;
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int flags;
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int type;
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struct tty_struct *tty;
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unsigned long timer;
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int timeout;
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int xmit_fifo_size;
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int custom_divisor;
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int x_char; /* xon/xoff characater */
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int event;
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int line;
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};
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/*
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* Events are used to schedule things to happen at timer-interrupt
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* time, instead of at rs interrupt time.
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*/
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#define RS_EVENT_READ_PROCESS 0
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#define RS_EVENT_WRITE_WAKEUP 1
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#define RS_EVENT_HUP_PGRP 2
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#define RS_EVENT_BREAK_INT 3
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#define RS_EVENT_DO_SAK 4
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/*
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* These are the UART port assignments, expressed as offsets from the base
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* register. These assignments should hold for any serial port based on
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* a 8250, 16450, or 16550(A).
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*/
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#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
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#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
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#define UART_DLL 0 /* Out: Devisor Latch Low (DLAB=1) */
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#define UART_DLM 1 /* Out: Devisor Latch High (DLAB=1) */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_MSR 6 /* In: Modem Status Register */
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#define UART_SCR 7 /* I/O: Scratch Register */
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/*
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* These are the definitions for the FIFO Control Register
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*/
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define UART_FCR_CLEAR_CMD (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)
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#define UART_FCR_SETUP_CMD (UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14)
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/*
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* These are the definitions for the Line Control Register
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*
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* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define UART_LCR_DLAB 0x80 /* Devisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even paraity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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/*
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* These are the definitions for the Interrupt Indentification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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