106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
#ifndef SYS_SERIAL_H
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#define SYS_SERIAL_H
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/*
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* Defines for PC AT serial port.
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*/
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/*
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* serial port addresses and IRQs
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*/
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#define PORT_0 0x03F8
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#define PORT_1 0x02F8
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#define IRQ_0 0x04
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#define IRQ_1 0x03
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/*
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* Definitions for INS8250 / 16550 chips
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*/
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/* defined as offsets from the port address (data port) */
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#define DAT 0 /* receive/transmit data */
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#define ICR 1 /* interrupt control register */
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#define ISR 2 /* interrupt status register */
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#define LCR 3 /* line control register */
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#define MCR 4 /* modem control register */
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#define LSR 5 /* line status register */
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#define MSR 6 /* modem status register */
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#define DLL 0 /* divisor latch (lsb) */
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#define DLH 1 /* divisor latch (msb) */
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/* ICR */
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#define RIEN 0x01 /* enable receiver interrupt */
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#define TIEN 0x02 /* enable transmitter interrupt */
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#define SIEN 0x04 /* enable receiver line status interrupt */
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#define MIEN 0x08 /* enable modem status interrupt */
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/* ISR */
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#define FFTMOUT 0x0c /* fifo rcvr timeout */
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#define RSTATUS 0x06 /* change in receiver line status */
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#define RxRDY 0x04 /* receiver data available */
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#define TxRDY 0x02 /* transmitter holding register empty */
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#define MSTATUS 0x00 /* change in modem status */
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/* LCR 3 */
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/* number of data bits per received/transmitted character */
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#define RXLEN 0x03
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#define STOP1 0x00
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#define STOP2 0x04
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#define PAREN 0x08
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#define PAREVN 0x10
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#define PARMARK 0x20
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#define SNDBRK 0x40
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#define DLAB 0x80
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/* baud rate definitions */
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#define ASY9600 12
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/* definitions for character length (data bits) in RXLEN field */
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#define BITS5 0x00
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#define BITS6 0x01
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#define BITS7 0x02
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#define BITS8 0x03
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/* MCR */
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#define DTR 0x01 /* bring up DTR */
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#define RTS 0x02 /* bring up RTS */
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#define OUT1 0x04
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#define OUT2 0x08
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#define LOOP 0x10 /* put chip into loopback state */
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/* LSR */
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#define RCA 0x01 /* receive char available */
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#define OVRRUN 0x02 /* receive overrun */
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#define PARERR 0x04 /* parity error */
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#define FRMERR 0x08 /* framing/CRC error */
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#define BRKDET 0x10 /* break detected (null char + frame error) */
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#define XHRE 0x20 /* transmit holding register empty */
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#define XSRE 0x40 /* transmit shift register empty */
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/* MSR */
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#define DCTS 0x01 /* CTS has changed state */
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#define DDSR 0x02 /* DSR has changed state */
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#define DRI 0x04 /* RI has changed state */
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#define DDCD 0x08 /* DCD has changed state */
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#define CTS 0x10 /* state of CTS */
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#define DSR 0x20 /* state of DSR */
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#define RI 0x40 /* state of RI */
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#define DCD 0x80 /* state of DCD */
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#define DELTAS(x) ((x)&(DCTS|DDSR|DRI|DDCD))
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#define STATES(x) ((x)(CTS|DSR|RI|DCD))
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#endif /* SYS_SERIAL_H */
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