61 lines
4.9 KiB
HTML
61 lines
4.9 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
|
|
<html>
|
|
|
|
<head>
|
|
<title>80386 Programmer's Reference Manual -- Opcode LOCK</title>
|
|
</head>
|
|
|
|
<body>
|
|
<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
|
|
<b>prev:</b><a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM"> LMSW Load Machine Status Word</a><br>
|
|
<b>next:</b><a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM"> LODS/LODSB/LODSW/LODSD Load String Operand</a>
|
|
<p>
|
|
<hr>
|
|
<p>
|
|
<h1>LOCK -- Assert LOCK# Signal Prefix</h1>
|
|
<pre>
|
|
|
|
|
|
|
|
Opcode Instruction Clocks Description
|
|
|
|
F0 LOCK 0 Assert LOCK# signal for the next instruction
|
|
</pre>
|
|
<h2>Description</h2>
|
|
The LOCK prefix causes the LOCK# signal of the 80386 to be asserted during execution of the instruction that follows it. In a multiprocessor environment, this signal can be used to ensure that the 80386 has exclusive use of any shared memory while LOCK# is asserted. The read-modify-write sequence typically used to implement test-and-set on the 80386 is the <a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS</a> instruction.
|
|
<p>The LOCK prefix functions only with the following instructions:
|
|
<pre>
|
|
|
|
|
|
|
|
<a href="BT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BT.HTM">BT</a>, <a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS</a>, <a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM">BTR</a>, <a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM">BTC</a> mem, reg/imm
|
|
<a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a> reg, mem
|
|
<a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a> mem, reg
|
|
<a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a>, <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a>, <a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM">ADC</a>, <a href="SBB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SBB.HTM">SBB</a>, <a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND</a>, <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a>, <a href="XOR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XOR.HTM">XOR</a> mem, reg/imm
|
|
<a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM">NOT</a>, <a href="NEG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NEG.HTM">NEG</a>, <a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC</a>, <a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a> mem
|
|
</pre>
|
|
An undefined opcode trap will be generated if a LOCK prefix is used with any instruction not listed above.
|
|
<p><a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a> always asserts LOCK# regardless of the presence or absence of the LOCK prefix.
|
|
<p>The integrity of the LOCK is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.
|
|
<p>Locked access is not assured if another 80386 processor is executing an instruction concurrently that has one of the following characteristics:
|
|
<ul>
|
|
<li>Is not preceded by a LOCK prefix
|
|
<li>Is not one of the instructions in the preceding list
|
|
<li>Specifies a memory operand that does not exactly overlap the destination operand. Locking is not guaranteed for partial overlap, even if one memory operand is wholly contained within another.
|
|
</ul>
|
|
<h2>Flags Affected</h2>
|
|
None
|
|
<h2>Protected Mode Exceptions</h2>
|
|
#UD if LOCK is used with an instruction not listed in the "Description" section above; other exceptions can be generated by the subsequent (locked) instruction
|
|
<h2>Real Address Mode Exceptions</h2>
|
|
Interrupt 6 if LOCK is used with an instruction not listed in the "Description" section above; exceptions can still be generated by the subsequent (locked) instruction
|
|
<h2>Virtual 8086 Mode Exceptions</h2>
|
|
#UD if LOCK is used with an instruction not listed in the "Description" section above; exceptions can still be generated by the subsequent (locked) instruction
|
|
<p>
|
|
<hr>
|
|
<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
|
|
<b>prev:</b><a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM"> LMSW Load Machine Status Word</a><br>
|
|
<b>next:</b><a href="LODS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LODS.HTM"> LODS/LODSB/LODSW/LODSD Load String Operand</a>
|
|
</body>
|
|
|