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<TITLE>Using as - M680x0 Dependent Features</TITLE>
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<P><HR><P>
<H1><A NAME="SEC214" HREF="as_toc.html#TOC214">M680x0 Dependent Features</A></H1>
<P>
<A NAME="IDX666"></A>
</P>
<H2><A NAME="SEC215" HREF="as_toc.html#TOC215">M680x0 Options</A></H2>
<P>
<A NAME="IDX667"></A>
<A NAME="IDX668"></A>
The Motorola 680x0 version of <CODE>as</CODE> has a few machine
dependent options.
</P>
<P>
<A NAME="IDX669"></A>
You can use the <SAMP>`-l'</SAMP> option to shorten the size of references to undefined
symbols. If you do not use the <SAMP>`-l'</SAMP> option, references to undefined
symbols are wide enough for a full <CODE>long</CODE> (32 bits). (Since
<CODE>as</CODE> cannot know where these symbols end up, <CODE>as</CODE> can
only allocate space for the linker to fill in later. Since <CODE>as</CODE>
does not know how far away these symbols are, it allocates as much space as it
can.) If you use this option, the references are only one word wide (16 bits).
This may be useful if you want the object file to be as small as possible, and
you know that the relevant symbols are always less than 17 bits away.
</P>
<P>
<A NAME="IDX670"></A>
For some configurations, especially those where the compiler normally
does not prepend an underscore to the names of user variables, the
assembler requires a <SAMP>`%'</SAMP> before any use of a register name. This
is intended to let the assembler distinguish between C variables and
functions named <SAMP>`a0'</SAMP> through <SAMP>`a7'</SAMP>, and so on. The <SAMP>`%'</SAMP> is
always accepted, but is not required for certain configurations, notably
<SAMP>`sun3'</SAMP>. The <SAMP>`--register-prefix-optional'</SAMP> option may be used
to permit omitting the <SAMP>`%'</SAMP> even for configurations for which it is
normally required. If this is done, it will generally be impossible to
refer to C variables and functions with the same names as register
names.
</P>
<P>
<A NAME="IDX671"></A>
Normally the character <SAMP>`|'</SAMP> is treated as a comment character, which
means that it can not be used in expressions. The <SAMP>`--bitwise-or'</SAMP>
option turns <SAMP>`|'</SAMP> into a normal character. In this mode, you must
either use C style comments, or start comments with a <SAMP>`#'</SAMP> character
at the beginning of a line.
</P>
<P>
<A NAME="IDX672"></A>
<A NAME="IDX673"></A>
If you use an addressing mode with a base register without specifying
the size, <CODE>as</CODE> will normally use the full 32 bit value.
For example, the addressing mode <SAMP>`%a0@(%d0)'</SAMP> is equivalent to
<SAMP>`%a0@(%d0:l)'</SAMP>. You may use the <SAMP>`--base-size-default-16'</SAMP>
option to tell <CODE>as</CODE> to default to using the 16 bit value.
In this case, <SAMP>`%a0@(%d0)'</SAMP> is equivalent to <SAMP>`%a0@(%d0:w)'</SAMP>.
You may use the <SAMP>`--base-size-default-32'</SAMP> option to restore the
default behaviour.
</P>
<P>
<A NAME="IDX674"></A>
<A NAME="IDX675"></A>
If you use an addressing mode with a displacement, and the value of the
displacement is not known, <CODE>as</CODE> will normally assume that
the value is 32 bits. For example, if the symbol <SAMP>`disp'</SAMP> has not
been defined, <CODE>as</CODE> will assemble the addressing mode
<SAMP>`%a0@(disp,%d0)'</SAMP> as though <SAMP>`disp'</SAMP> is a 32 bit value. You may
use the <SAMP>`--disp-size-default-16'</SAMP> option to tell <CODE>as</CODE>
to instead assume that the displacement is 16 bits. In this case,
<CODE>as</CODE> will assemble <SAMP>`%a0@(disp,%d0)'</SAMP> as though
<SAMP>`disp'</SAMP> is a 16 bit value. You may use the
<SAMP>`--disp-size-default-32'</SAMP> option to restore the default behaviour.
</P>
<P>
<A NAME="IDX676"></A>
<A NAME="IDX677"></A>
<A NAME="IDX678"></A>
<CODE>as</CODE> can assemble code for several different members of the
Motorola 680x0 family. The default depends upon how <CODE>as</CODE>
was configured when it was built; normally, the default is to assemble
code for the 68020 microprocessor. The following options may be used to
change the default. These options control which instructions and
addressing modes are permitted. The members of the 680x0 family are
very similar. For detailed information about the differences, see the
Motorola manuals.
</P>
<DL COMPACT>
<DT><SAMP>`-m68000'</SAMP>
<DD>
<DT><SAMP>`-m68ec000'</SAMP>
<DD>
<DT><SAMP>`-m68hc000'</SAMP>
<DD>
<DT><SAMP>`-m68hc001'</SAMP>
<DD>
<DT><SAMP>`-m68008'</SAMP>
<DD>
<DT><SAMP>`-m68302'</SAMP>
<DD>
<DT><SAMP>`-m68306'</SAMP>
<DD>
<DT><SAMP>`-m68307'</SAMP>
<DD>
<DT><SAMP>`-m68322'</SAMP>
<DD>
<DT><SAMP>`-m68356'</SAMP>
<DD>
Assemble for the 68000. <SAMP>`-m68008'</SAMP>, <SAMP>`-m68302'</SAMP>, and so on are synonyms
for <SAMP>`-m68000'</SAMP>, since the chips are the same from the point of view
of the assembler.
<DT><SAMP>`-m68010'</SAMP>
<DD>
Assemble for the 68010.
<DT><SAMP>`-m68020'</SAMP>
<DD>
<DT><SAMP>`-m68ec020'</SAMP>
<DD>
Assemble for the 68020. This is normally the default.
<DT><SAMP>`-m68030'</SAMP>
<DD>
<DT><SAMP>`-m68ec030'</SAMP>
<DD>
Assemble for the 68030.
<DT><SAMP>`-m68040'</SAMP>
<DD>
<DT><SAMP>`-m68ec040'</SAMP>
<DD>
Assemble for the 68040.
<DT><SAMP>`-m68060'</SAMP>
<DD>
<DT><SAMP>`-m68ec060'</SAMP>
<DD>
Assemble for the 68060.
<DT><SAMP>`-mcpu32'</SAMP>
<DD>
<DT><SAMP>`-m68330'</SAMP>
<DD>
<DT><SAMP>`-m68331'</SAMP>
<DD>
<DT><SAMP>`-m68332'</SAMP>
<DD>
<DT><SAMP>`-m68333'</SAMP>
<DD>
<DT><SAMP>`-m68334'</SAMP>
<DD>
<DT><SAMP>`-m68336'</SAMP>
<DD>
<DT><SAMP>`-m68340'</SAMP>
<DD>
<DT><SAMP>`-m68341'</SAMP>
<DD>
<DT><SAMP>`-m68349'</SAMP>
<DD>
<DT><SAMP>`-m68360'</SAMP>
<DD>
Assemble for the CPU32 family of chips.
<DT><SAMP>`-m5200'</SAMP>
<DD>
Assemble for the ColdFire family of chips.
<DT><SAMP>`-m68881'</SAMP>
<DD>
<DT><SAMP>`-m68882'</SAMP>
<DD>
Assemble 68881 floating point instructions. This is the default for the
68020, 68030, and the CPU32. The 68040 and 68060 always support
floating point instructions.
<DT><SAMP>`-mno-68881'</SAMP>
<DD>
Do not assemble 68881 floating point instructions. This is the default
for 68000 and the 68010. The 68040 and 68060 always support floating
point instructions, even if this option is used.
<DT><SAMP>`-m68851'</SAMP>
<DD>
Assemble 68851 MMU instructions. This is the default for the 68020,
68030, and 68060. The 68040 accepts a somewhat different set of MMU
instructions; <SAMP>`-m68851'</SAMP> and <SAMP>`-m68040'</SAMP> should not be used
together.
<DT><SAMP>`-mno-68851'</SAMP>
<DD>
Do not assemble 68851 MMU instructions. This is the default for the
68000, 68010, and the CPU32. The 68040 accepts a somewhat different set
of MMU instructions.
</DL>
<H2><A NAME="SEC216" HREF="as_toc.html#TOC216">Syntax</A></H2>
<P>
<A NAME="IDX679"></A>
This syntax for the Motorola 680x0 was developed at MIT.
</P>
<P>
<A NAME="IDX680"></A>
<A NAME="IDX681"></A>
<A NAME="IDX682"></A>
<A NAME="IDX683"></A>
The 680x0 version of <CODE>as</CODE> uses instructions names and
syntax compatible with the Sun assembler. Intervening periods are
ignored; for example, <SAMP>`movl'</SAMP> is equivalent to <SAMP>`mov.l'</SAMP>.
</P>
<P>
In the following table <VAR>apc</VAR> stands for any of the address registers
(<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP>), the program counter (<SAMP>`%pc'</SAMP>), the
zero-address relative to the program counter (<SAMP>`%zpc'</SAMP>), a suppressed
address register (<SAMP>`%za0'</SAMP> through <SAMP>`%za7'</SAMP>), or it may be omitted
entirely. The use of <VAR>size</VAR> means one of <SAMP>`w'</SAMP> or <SAMP>`l'</SAMP>, and
it may be omitted, along with the leading colon, unless a scale is also
specified. The use of <VAR>scale</VAR> means one of <SAMP>`1'</SAMP>, <SAMP>`2'</SAMP>,
<SAMP>`4'</SAMP>, or <SAMP>`8'</SAMP>, and it may always be omitted along with the
leading colon.
</P>
<P>
<A NAME="IDX684"></A>
<A NAME="IDX685"></A>
The following addressing modes are understood:
<DL COMPACT>
<DT><EM>Immediate</EM>
<DD>
<SAMP>`#<VAR>number</VAR>'</SAMP>
<DT><EM>Data Register</EM>
<DD>
<SAMP>`%d0'</SAMP> through <SAMP>`%d7'</SAMP>
<DT><EM>Address Register</EM>
<DD>
<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP><BR>
<SAMP>`%a7'</SAMP> is also known as <SAMP>`%sp'</SAMP>, i.e. the Stack Pointer. <CODE>%a6</CODE>
is also known as <SAMP>`%fp'</SAMP>, the Frame Pointer.
<DT><EM>Address Register Indirect</EM>
<DD>
<SAMP>`%a0@'</SAMP> through <SAMP>`%a7@'</SAMP>
<DT><EM>Address Register Postincrement</EM>
<DD>
<SAMP>`%a0@+'</SAMP> through <SAMP>`%a7@+'</SAMP>
<DT><EM>Address Register Predecrement</EM>
<DD>
<SAMP>`%a0@-'</SAMP> through <SAMP>`%a7@-'</SAMP>
<DT><EM>Indirect Plus Offset</EM>
<DD>
<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>)'</SAMP>
<DT><EM>Index</EM>
<DD>
<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)'</SAMP>
The <VAR>number</VAR> may be omitted.
<DT><EM>Postindex</EM>
<DD>
<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>)@(<VAR>onumber</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)'</SAMP>
The <VAR>onumber</VAR> or the <VAR>register</VAR>, but not both, may be omitted.
<DT><EM>Preindex</EM>
<DD>
<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)@(<VAR>onumber</VAR>)'</SAMP>
The <VAR>number</VAR> may be omitted. Omitting the <VAR>register</VAR> produces
the Postindex addressing mode.
<DT><EM>Absolute</EM>
<DD>
<SAMP>`<VAR>symbol</VAR>'</SAMP>, or <SAMP>`<VAR>digits</VAR>'</SAMP>, optionally followed by
<SAMP>`:b'</SAMP>, <SAMP>`:w'</SAMP>, or <SAMP>`:l'</SAMP>.
</DL>
<H2><A NAME="SEC217" HREF="as_toc.html#TOC217">Motorola Syntax</A></H2>
<P>
<A NAME="IDX686"></A>
<A NAME="IDX687"></A>
</P>
<P>
The standard Motorola syntax for this chip differs from the syntax
already discussed (see section <A HREF="as_18.html#SEC216">Syntax</A>). <CODE>as</CODE> can
accept Motorola syntax for operands, even if MIT syntax is used for
other operands in the same instruction. The two kinds of syntax are
fully compatible.
</P>
<P>
In the following table <VAR>apc</VAR> stands for any of the address registers
(<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP>), the program counter (<SAMP>`%pc'</SAMP>), the
zero-address relative to the program counter (<SAMP>`%zpc'</SAMP>), or a
suppressed address register (<SAMP>`%za0'</SAMP> through <SAMP>`%za7'</SAMP>). The use
of <VAR>size</VAR> means one of <SAMP>`w'</SAMP> or <SAMP>`l'</SAMP>, and it may always be
omitted along with the leading dot. The use of <VAR>scale</VAR> means one of
<SAMP>`1'</SAMP>, <SAMP>`2'</SAMP>, <SAMP>`4'</SAMP>, or <SAMP>`8'</SAMP>, and it may always be omitted
along with the leading asterisk.
</P>
<P>
The following additional addressing modes are understood:
</P>
<DL COMPACT>
<DT><EM>Address Register Indirect</EM>
<DD>
<SAMP>`(%a0)'</SAMP> through <SAMP>`(%a7)'</SAMP><BR>
<SAMP>`%a7'</SAMP> is also known as <SAMP>`%sp'</SAMP>, i.e. the Stack Pointer. <CODE>%a6</CODE>
is also known as <SAMP>`%fp'</SAMP>, the Frame Pointer.
<DT><EM>Address Register Postincrement</EM>
<DD>
<SAMP>`(%a0)+'</SAMP> through <SAMP>`(%a7)+'</SAMP>
<DT><EM>Address Register Predecrement</EM>
<DD>
<SAMP>`-(%a0)'</SAMP> through <SAMP>`-(%a7)'</SAMP>
<DT><EM>Indirect Plus Offset</EM>
<DD>
<SAMP>`<VAR>number</VAR>(<VAR>%a0</VAR>)'</SAMP> through <SAMP>`<VAR>number</VAR>(<VAR>%a7</VAR>)'</SAMP>,
or <SAMP>`<VAR>number</VAR>(<VAR>%pc</VAR>)'</SAMP>.
The <VAR>number</VAR> may also appear within the parentheses, as in
<SAMP>`(<VAR>number</VAR>,<VAR>%a0</VAR>)'</SAMP>. When used with the <VAR>pc</VAR>, the
<VAR>number</VAR> may be omitted (with an address register, omitting the
<VAR>number</VAR> produces Address Register Indirect mode).
<DT><EM>Index</EM>
<DD>
<SAMP>`<VAR>number</VAR>(<VAR>apc</VAR>,<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>)'</SAMP>
The <VAR>number</VAR> may be omitted, or it may appear within the
parentheses. The <VAR>apc</VAR> may be omitted. The <VAR>register</VAR> and the
<VAR>apc</VAR> may appear in either order. If both <VAR>apc</VAR> and
<VAR>register</VAR> are address registers, and the <VAR>size</VAR> and <VAR>scale</VAR>
are omitted, then the first register is taken as the base register, and
the second as the index register.
<DT><EM>Postindex</EM>
<DD>
<SAMP>`([<VAR>number</VAR>,<VAR>apc</VAR>],<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>,<VAR>onumber</VAR>)'</SAMP>
The <VAR>onumber</VAR>, or the <VAR>register</VAR>, or both, may be omitted.
Either the <VAR>number</VAR> or the <VAR>apc</VAR> may be omitted, but not both.
<DT><EM>Preindex</EM>
<DD>
<SAMP>`([<VAR>number</VAR>,<VAR>apc</VAR>,<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>],<VAR>onumber</VAR>)'</SAMP>
The <VAR>number</VAR>, or the <VAR>apc</VAR>, or the <VAR>register</VAR>, or any two of
them, may be omitted. The <VAR>onumber</VAR> may be omitted. The
<VAR>register</VAR> and the <VAR>apc</VAR> may appear in either order. If both
<VAR>apc</VAR> and <VAR>register</VAR> are address registers, and the <VAR>size</VAR>
and <VAR>scale</VAR> are omitted, then the first register is taken as the
base register, and the second as the index register.
</DL>
<H2><A NAME="SEC218" HREF="as_toc.html#TOC218">Floating Point</A></H2>
<P>
<A NAME="IDX688"></A>
<A NAME="IDX689"></A>
Packed decimal (P) format floating literals are not supported.
Feel free to add the code!
</P>
<P>
The floating point formats generated by directives are these.
</P>
<DL COMPACT>
<DT><CODE>.float</CODE>
<DD>
<A NAME="IDX690"></A>
<CODE>Single</CODE> precision floating point constants.
<A NAME="IDX691"></A>
<DT><CODE>.double</CODE>
<DD>
<CODE>Double</CODE> precision floating point constants.
<A NAME="IDX692"></A>
<A NAME="IDX693"></A>
<DT><CODE>.extend</CODE>
<DD>
<DT><CODE>.ldouble</CODE>
<DD>
<CODE>Extended</CODE> precision (<CODE>long double</CODE>) floating point constants.
</DL>
<H2><A NAME="SEC219" HREF="as_toc.html#TOC219">680x0 Machine Directives</A></H2>
<P>
<A NAME="IDX694"></A>
<A NAME="IDX695"></A>
In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.
</P>
<DL COMPACT>
<DT><CODE>.data1</CODE>
<DD>
<A NAME="IDX696"></A>
This directive is identical to a <CODE>.data 1</CODE> directive.
<A NAME="IDX697"></A>
<DT><CODE>.data2</CODE>
<DD>
This directive is identical to a <CODE>.data 2</CODE> directive.
<A NAME="IDX698"></A>
<DT><CODE>.even</CODE>
<DD>
This directive is a special case of the <CODE>.align</CODE> directive; it
aligns the output to an even byte boundary.
<A NAME="IDX699"></A>
<DT><CODE>.skip</CODE>
<DD>
This directive is identical to a <CODE>.space</CODE> directive.
</DL>
<H2><A NAME="SEC220" HREF="as_toc.html#TOC220">Opcodes</A></H2>
<P>
<A NAME="IDX700"></A>
<A NAME="IDX701"></A>
<A NAME="IDX702"></A>
</P>
<H3><A NAME="SEC221" HREF="as_toc.html#TOC221">Branch Improvement</A></H3>
<P>
<A NAME="IDX703"></A>
<A NAME="IDX704"></A>
<A NAME="IDX705"></A>
<A NAME="IDX706"></A>
Certain pseudo opcodes are permitted for branch instructions.
They expand to the shortest branch instruction that reach the
target. Generally these mnemonics are made by substituting <SAMP>`j'</SAMP> for
<SAMP>`b'</SAMP> at the start of a Motorola mnemonic.
</P>
<P>
The following table summarizes the pseudo-operations. A <CODE>*</CODE> flags
cases that are more fully described after the table:
</P>
<PRE>
Displacement
+-------------------------------------------------
| 68020 68000/10
Pseudo-Op |BYTE WORD LONG LONG non-PC relative
+-------------------------------------------------
jbsr |bsrs bsr bsrl jsr jsr
jra |bras bra bral jmp jmp
* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
* dbXX |dbXX dbXX dbXX; bra; jmpl
* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
XX: condition
NX: negative of condition XX
</PRE>
<P>
<CODE>*</CODE>---see full description below
</P>
<DL COMPACT>
<DT><CODE>jbsr</CODE>
<DD>
<DT><CODE>jra</CODE>
<DD>
These are the simplest jump pseudo-operations; they always map to one
particular machine instruction, depending on the displacement to the
branch target.
<DT><CODE>j<VAR>XX</VAR></CODE>
<DD>
Here, <SAMP>`j<VAR>XX</VAR>'</SAMP> stands for an entire family of pseudo-operations,
where <VAR>XX</VAR> is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
<PRE>
jhi jls jcc jcs jne jeq jvc
jvs jpl jmi jge jlt jgt jle
</PRE>
For the cases of non-PC relative displacements and long displacements on
the 68000 or 68010, <CODE>as</CODE> issues a longer code fragment in terms of
<VAR>NX</VAR>, the opposite condition to <VAR>XX</VAR>. For example, for the
non-PC relative case:
<PRE>
j<VAR>XX</VAR> foo
</PRE>
gives
<PRE>
b<VAR>NX</VAR>s oof
jmp foo
oof:
</PRE>
<DT><CODE>db<VAR>XX</VAR></CODE>
<DD>
The full family of pseudo-operations covered here is
<PRE>
dbhi dbls dbcc dbcs dbne dbeq dbvc
dbvs dbpl dbmi dbge dblt dbgt dble
dbf dbra dbt
</PRE>
Other than for word and byte displacements, when the source reads
<SAMP>`db<VAR>XX</VAR> foo'</SAMP>, <CODE>as</CODE> emits
<PRE>
db<VAR>XX</VAR> oo1
bra oo2
oo1:jmpl foo
oo2:
</PRE>
<DT><CODE>fj<VAR>XX</VAR></CODE>
<DD>
This family includes
<PRE>
fjne fjeq fjge fjlt fjgt fjle fjf
fjt fjgl fjgle fjnge fjngl fjngle fjngt
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
fjor fjseq fjsf fjsne fjst fjueq fjuge
fjugt fjule fjult fjun
</PRE>
For branch targets that are not PC relative, <CODE>as</CODE> emits
<PRE>
fb<VAR>NX</VAR> oof
jmp foo
oof:
</PRE>
when it encounters <SAMP>`fj<VAR>XX</VAR> foo'</SAMP>.
</DL>
<H3><A NAME="SEC222" HREF="as_toc.html#TOC222">Special Characters</A></H3>
<P>
<A NAME="IDX707"></A>
<A NAME="IDX708"></A>
<A NAME="IDX709"></A>
<A NAME="IDX710"></A>
<A NAME="IDX711"></A>
<A NAME="IDX712"></A>
The immediate character is <SAMP>`#'</SAMP> for Sun compatibility. The
line-comment character is <SAMP>`|'</SAMP> (unless the <SAMP>`--bitwise-or'</SAMP>
option is used). If a <SAMP>`#'</SAMP> appears at the beginning of a line, it
is treated as a comment unless it looks like <SAMP>`# line file'</SAMP>, in
which case it is treated normally.
</P>
<P><HR><P>
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