1002 lines
44 KiB
Plaintext
1002 lines
44 KiB
Plaintext
This is Info file gcc.info, produced by Makeinfo-1.47 from the input
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file gcc.texi.
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This file documents the use and the internals of the GNU compiler.
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Copyright (C) 1988, 1989, 1992 Free Software Foundation, Inc.
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Permission is granted to make and distribute verbatim copies of this
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manual provided the copyright notice and this permission notice are
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preserved on all copies.
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Permission is granted to copy and distribute modified versions of
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this manual under the conditions for verbatim copying, provided also
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that the sections entitled "GNU General Public License" and "Boycott"
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are included exactly as in the original, and provided that the entire
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resulting derived work is distributed under the terms of a permission
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notice identical to this one.
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Permission is granted to copy and distribute translations of this
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manual into another language, under the above conditions for modified
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versions, except that the sections entitled "GNU General Public
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License" and "Boycott", and this permission notice, may be included in
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translations approved by the Free Software Foundation instead of in the
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original English.
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File: gcc.info, Node: Expander Definitions, Next: Insn Splitting, Prev: Peephole Definitions, Up: Machine Desc
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Defining RTL Sequences for Code Generation
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==========================================
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On some target machines, some standard pattern names for RTL
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generation cannot be handled with single insn, but a sequence of RTL
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insns can represent them. For these target machines, you can write a
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`define_expand' to specify how to generate the sequence of RTL.
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A `define_expand' is an RTL expression that looks almost like a
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`define_insn'; but, unlike the latter, a `define_expand' is used only
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for RTL generation and it can produce more than one RTL insn.
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A `define_expand' RTX has four operands:
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* The name. Each `define_expand' must have a name, since the only
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use for it is to refer to it by name.
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* The RTL template. This is just like the RTL template for a
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`define_peephole' in that it is a vector of RTL expressions each
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being one insn.
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* The condition, a string containing a C expression. This
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expression is used to express how the availability of this pattern
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depends on subclasses of target machine, selected by command-line
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options when GNU CC is run. This is just like the condition of a
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`define_insn' that has a standard name.
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* The preparation statements, a string containing zero or more C
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statements which are to be executed before RTL code is generated
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from the RTL template.
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Usually these statements prepare temporary registers for use as
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internal operands in the RTL template, but they can also generate
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RTL insns directly by calling routines such as `emit_insn', etc.
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Any such insns precede the ones that come from the RTL template.
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Every RTL insn emitted by a `define_expand' must match some
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`define_insn' in the machine description. Otherwise, the compiler will
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crash when trying to generate code for the insn or trying to optimize
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it.
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The RTL template, in addition to controlling generation of RTL insns,
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also describes the operands that need to be specified when this pattern
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is used. In particular, it gives a predicate for each operand.
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A true operand, which needs to be specified in order to generate RTL
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from the pattern, should be described with a `match_operand' in its
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first occurrence in the RTL template. This enters information on the
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operand's predicate into the tables that record such things. GNU CC
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uses the information to preload the operand into a register if that is
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required for valid RTL code. If the operand is referred to more than
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once, subsequent references should use `match_dup'.
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The RTL template may also refer to internal "operands" which are
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temporary registers or labels used only within the sequence made by the
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`define_expand'. Internal operands are substituted into the RTL
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template with `match_dup', never with `match_operand'. The values of
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the internal operands are not passed in as arguments by the compiler
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when it requests use of this pattern. Instead, they are computed
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within the pattern, in the preparation statements. These statements
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compute the values and store them into the appropriate elements of
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`operands' so that `match_dup' can find them.
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There are two special macros defined for use in the preparation
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statements: `DONE' and `FAIL'. Use them with a following semicolon, as
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a statement.
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`DONE'
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Use the `DONE' macro to end RTL generation for the pattern. The
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only RTL insns resulting from the pattern on this occasion will be
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those already emitted by explicit calls to `emit_insn' within the
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preparation statements; the RTL template will not be generated.
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`FAIL'
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Make the pattern fail on this occasion. When a pattern fails, it
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means that the pattern was not truly available. The calling
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routines in the compiler will try other strategies for code
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generation using other patterns.
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Failure is currently supported only for binary (addition,
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multiplication, shifting, etc.) and bitfield (`extv', `extzv', and
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`insv') operations.
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Here is an example, the definition of left-shift for the SPUR chip:
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(define_expand "ashlsi3"
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[(set (match_operand:SI 0 "register_operand" "")
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(ashift:SI
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(match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT
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|| (unsigned) INTVAL (operands[2]) > 3)
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FAIL;
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}")
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This example uses `define_expand' so that it can generate an RTL insn
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for shifting when the shift-count is in the supported range of 0 to 3
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but fail in other cases where machine insns aren't available. When it
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fails, the compiler tries another strategy using different patterns
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(such as, a library call).
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If the compiler were able to handle nontrivial condition-strings in
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patterns with names, then it would be possible to use a `define_insn'
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in that case. Here is another case (zero-extension on the 68000) which
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makes more use of the power of `define_expand':
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "general_operand" "")
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(const_int 0))
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(set (strict_low_part
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(subreg:HI
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(match_dup 0)
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0))
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(match_operand:HI 1 "general_operand" ""))]
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""
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"operands[1] = make_safe_from (operands[1], operands[0]);")
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Here two RTL insns are generated, one to clear the entire output operand
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and the other to copy the input operand into its low half. This
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sequence is incorrect if the input operand refers to [the old value of]
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the output operand, so the preparation statement makes sure this isn't
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so. The function `make_safe_from' copies the `operands[1]' into a
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temporary register if it refers to `operands[0]'. It does this by
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emitting another RTL insn.
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Finally, a third example shows the use of an internal operand.
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Zero-extension on the SPUR chip is done by `and'-ing the result against
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a halfword mask. But this mask cannot be represented by a `const_int'
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because the constant value is too large to be legitimate on this
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machine. So it must be copied into a register with `force_reg' and
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then the register used in the `and'.
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(and:SI (subreg:SI
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(match_operand:HI 1 "register_operand" "")
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0)
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(match_dup 2)))]
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""
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"operands[2]
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= force_reg (SImode, gen_rtx (CONST_INT,
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VOIDmode, 65535)); ")
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*Note:* If the `define_expand' is used to serve a standard binary or
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unary arithmetic operation or a bitfield operation, then the last insn
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it generates must not be a `code_label', `barrier' or `note'. It must
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be an `insn', `jump_insn' or `call_insn'. If you don't need a real insn
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at the end, emit an insn to copy the result of the operation into
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itself. Such an insn will generate no code, but it can avoid problems
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in the compiler.
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File: gcc.info, Node: Insn Splitting, Next: Insn Attributes, Prev: Expander Definitions, Up: Machine Desc
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Splitting Instructions into Multiple Instructions
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=================================================
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There are two cases where you should specify how to split a pattern
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into multiple insns. On machines that have instructions requiring delay
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slots (*note Delay Slots::.) or that have instructions whose output is
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not available for multiple cycles (*note Function Units::.), the
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compiler phases that optimize these cases need to be able to move insns
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into one-cycle delay slots. However, some insns may generate more than
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one machine instruction. These insns cannot be placed into a delay
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slot.
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Often you can rewrite the single insn as a list of individual insns,
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each corresponding to one machine instruction. The disadvantage of
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doing so is that it will cause the compilation to be slower and require
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more space. If the resulting insns are too complex, it may also
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suppress some optimizations. The compiler splits the insn if there is a
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reason to believe that it might improve instruction or delay slot
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scheduling.
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The insn combiner phase also splits putative insns. If three insns
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are merged into one insn with a complex expression that cannot be
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matched by some `define_insn' pattern, the combiner phase attempts to
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split the complex pattern into two insns that are recognized. Usually
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it can break the complex pattern into two patterns by splitting out some
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subexpression. However, in some other cases, such as performing an
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addition of a large constant in two insns on a RISC machine, the way to
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split the addition into two insns is machine-dependent.
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The `define_split' definition tells the compiler how to split a
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complex insn into several simpler insns. It looks like this:
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(define_split
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[INSN-PATTERN]
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"CONDITION"
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[NEW-INSN-PATTERN-1
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NEW-INSN-PATTERN-2
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...]
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"PREPARATION STATEMENTS")
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INSN-PATTERN is a pattern that needs to be split and CONDITION is
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the final condition to be tested, as in a `define_insn'. When an insn
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matching INSN-PATTERN and satisfying CONDITION is found, it is replaced
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in the insn list with the insns given by NEW-INSN-PATTERN-1,
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NEW-INSN-PATTERN-2, etc.
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The PREPARATION STATEMENTS are similar to those specified for
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`define_expand' (*note Expander Definitions::.) and are executed before
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the new RTL is generated to prepare for the generated code or emit some
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insns whose pattern is not fixed.
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Patterns are matched against INSN-PATTERN in two different
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circumstances. If an insn needs to be split for delay slot scheduling
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or insn scheduling, the insn is already known to be valid, which means
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that it must have been matched by some `define_insn' and, if
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`reload_completed' is non-zero, is known to satisfy the constraints of
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that `define_insn'. In that case, the new insn patterns must also be
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insns that are matched by some `define_insn' and, if `reload_completed'
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is non-zero, must also satisfy the constraints of those definitions.
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As an example of this usage of `define_split', consider the following
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example from `a29k.md', which splits a `sign_extend' from `HImode' to
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`SImode' into a pair of shift insns:
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(define_split
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[(set (match_operand:SI 0 "gen_reg_operand" "")
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(sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
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""
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[(set (match_dup 0)
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(ashift:SI (match_dup 1)
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(const_int 16)))
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(set (match_dup 0)
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(ashiftrt:SI (match_dup 0)
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(const_int 16)))]
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"
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{ operands[1] = gen_lowpart (SImode, operands[1]); }")
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When the combiner phase tries to split an insn pattern, it is always
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the case that the pattern is *not* matched by any `define_insn'. The
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combiner pass first tries to split a single `set' expression and then
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the same `set' expression inside a `parallel', but followed by a
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`clobber' of a pseudo-reg to use as a scratch register. In these
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cases, the combiner expects exactly two new insn patterns to be
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generated. It will verify that these patterns match some `define_insn'
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definitions, so you need not do this test in the `define_split' (of
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course, there is no point in writing a `define_split' that will never
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produce insns that match).
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Here is an example of this use of `define_split', taken from
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`rs6000.md':
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(define_split
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[(set (match_operand:SI 0 "gen_reg_operand" "")
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(plus:SI (match_operand:SI 1 "gen_reg_operand" "")
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(match_operand:SI 2 "non_add_cint_operand" "")))]
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""
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[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
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"
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{
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int low = INTVAL (operands[2]) & 0xffff;
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int high = (unsigned) INTVAL (operands[2]) >> 16;
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if (low & 0x8000)
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high++, low |= 0xffff0000;
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operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
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operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
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}")
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Here the predicate `non_add_cint_operand' matches any `const_int'
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that is *not* a valid operand of a single add insn. Write the add with
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the smaller displacement is written so that it can be substituted into
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the address of a subsequent operation.
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An example that uses a scratch register, from the same file,
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generates an equality comparison of a register and a large constant:
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(define_split
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[(set (match_operand:CC 0 "cc_reg_operand" "")
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(compare:CC (match_operand:SI 1 "gen_reg_operand" "")
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(match_operand:SI 2 "non_short_cint_operand" "")))
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(clobber (match_operand:SI 3 "gen_reg_operand" ""))]
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"find_single_use (operands[0], insn, 0)
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&& (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
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|| GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
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[(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
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(set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
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"
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{
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/* Get the constant we are comparing against, C, and see what it looks like
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sign-extended to 16 bits. Then see what constant could be XOR'ed
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with C to get the sign-extended value. */
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int c = INTVAL (operands[2]);
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int sextc = (c << 16) >> 16;
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int xorv = c ^ sextc;
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operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
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operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
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}")
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To avoid confusion, don't write a single `define_split' that accepts
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some insns that match some `define_insn' as well as some insns that
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don't. Instead, write two separate `define_split' definitions, one for
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the insns that are valid and one for the insns that are not valid.
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File: gcc.info, Node: Insn Attributes, Prev: Insn Splitting, Up: Machine Desc
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Instruction Attributes
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======================
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In addition to describing the instruction supported by the target
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machine, the `md' file also defines a group of "attributes" and a set of
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values for each. Every generated insn is assigned a value for each
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attribute. One possible attribute would be the effect that the insn has
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on the machine's condition code. This attribute can then be used by
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`NOTICE_UPDATE_CC' to track the condition codes.
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* Menu:
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* Defining Attributes:: Specifying attributes and their values.
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* Expressions:: Valid expressions for attribute values.
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* Tagging Insns:: Assigning attribute values to insns.
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* Attr Example:: An example of assigning attributes.
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* Insn Lengths:: Computing the length of insns.
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* Constant Attributes:: Defining attributes that are constant.
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* Delay Slots:: Defining delay slots required for a machine.
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* Function Units:: Specifying information for insn scheduling.
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File: gcc.info, Node: Defining Attributes, Next: Expressions, Prev: Insn Attributes, Up: Insn Attributes
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Defining Attributes and their Values
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------------------------------------
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The `define_attr' expression is used to define each attribute
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required by the target machine. It looks like:
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(define_attr NAME LIST-OF-VALUES DEFAULT)
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NAME is a string specifying the name of the attribute being defined.
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LIST-OF-VALUES is either a string that specifies a comma-separated
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list of values that can be assigned to the attribute, or a null string
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to indicate that the attribute takes numeric values.
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DEFAULT is an attribute expression that gives the value of this
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attribute for insns that match patterns whose definition does not
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include an explicit value for this attribute. *Note Attr Example::,
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for more information on the handling of defaults. *Note Constant
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Attributes::, for information on attributes that do not depend on any
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particular insn.
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For each defined attribute, a number of definitions are written to
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the `insn-attr.h' file. For cases where an explicit set of values is
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specified for an attribute, the following are defined:
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* A `#define' is written for the symbol `HAVE_ATTR_NAME'.
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* An enumeral class is defined for `attr_NAME' with elements of the
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form `UPPER-NAME_UPPER-VALUE' where the attribute name and value
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are first converted to upper case.
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* A function `get_attr_NAME' is defined that is passed an insn and
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returns the attribute value for that insn.
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For example, if the following is present in the `md' file:
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(define_attr "type" "branch,fp,load,store,arith" ...)
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the following lines will be written to the file `insn-attr.h'.
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#define HAVE_ATTR_type
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enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
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TYPE_STORE, TYPE_ARITH};
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extern enum attr_type get_attr_type ();
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If the attribute takes numeric values, no `enum' type will be
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defined and the function to obtain the attribute's value will return
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`int'.
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File: gcc.info, Node: Expressions, Next: Tagging Insns, Prev: Defining Attributes, Up: Insn Attributes
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Attribute Expressions
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---------------------
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RTL expressions used to define attributes use the codes described
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above plus a few specific to attribute definitions, to be discussed
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below. Attribute value expressions must have one of the following forms:
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`(const_int I)'
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The integer I specifies the value of a numeric attribute. I must
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be non-negative.
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The value of a numeric attribute can be specified either with a
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`const_int' or as an integer represented as a string in
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`const_string', `eq_attr' (see below), and `set_attr' (*note
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Tagging Insns::.) expressions.
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`(const_string VALUE)'
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The string VALUE specifies a constant attribute value. If VALUE is
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specified as `"*"', it means that the default value of the
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attribute is to be used for the insn containing this expression.
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`"*"' obviously cannot be used in the DEFAULT expression of a
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`define_attr'.
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If the attribute whose value is being specified is numeric, VALUE
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must be a string containing a non-negative integer (normally
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`const_int' would be used in this case). Otherwise, it must
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contain one of the valid values for the attribute.
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`(if_then_else TEST TRUE-VALUE FALSE-VALUE)'
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TEST specifies an attribute test, whose format is defined below.
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The value of this expression is TRUE-VALUE if TEST is true,
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otherwise it is FALSE-VALUE.
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`(cond [TEST1 VALUE1 ...] DEFAULT)'
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The first operand of this expression is a vector containing an even
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number of expressions and consisting of pairs of TEST and VALUE
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expressions. The value of the `cond' expression is that of the
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VALUE corresponding to the first true TEST expression. If none of
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the TEST expressions are true, the value of the `cond' expression
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is that of the DEFAULT expression.
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TEST expressions can have one of the following forms:
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`(const_int I)'
|
||
This test is true if I is non-zero and false otherwise.
|
||
|
||
`(not TEST)'
|
||
`(ior TEST1 TEST2)'
|
||
`(and TEST1 TEST2)'
|
||
These tests are true if the indicated logical function is true.
|
||
|
||
`(match_operand:M N PRED CONSTRAINTS)'
|
||
This test is true if operand N of the insn whose attribute value
|
||
is being determined has mode M (this part of the test is ignored
|
||
if M is `VOIDmode') and the function specified by the string PRED
|
||
returns a non-zero value when passed operand N and mode M (this
|
||
part of the test is ignored if PRED is the null string).
|
||
|
||
The CONSTRAINTS operand is ignored and should be the null string.
|
||
|
||
`(le ARITH1 ARITH2)'
|
||
`(leu ARITH1 ARITH2)'
|
||
`(lt ARITH1 ARITH2)'
|
||
`(ltu ARITH1 ARITH2)'
|
||
`(gt ARITH1 ARITH2)'
|
||
`(gtu ARITH1 ARITH2)'
|
||
`(ge ARITH1 ARITH2)'
|
||
`(geu ARITH1 ARITH2)'
|
||
`(ne ARITH1 ARITH2)'
|
||
`(eq ARITH1 ARITH2)'
|
||
These tests are true if the indicated comparison of the two
|
||
arithmetic expressions is true. Arithmetic expressions are formed
|
||
with `plus', `minus', `mult', `div', `mod', `abs', `neg', `and',
|
||
`ior', `xor', `not', `lshift', `ashift', `lshiftrt', and `ashiftrt'
|
||
expressions.
|
||
|
||
`const_int' and `symbol_ref' are always valid terms (*note Insn
|
||
Lengths::.,for additional forms). `symbol_ref' is a string
|
||
denoting a C expression that yields an `int' when evaluated by the
|
||
`get_attr_...' routine. It should normally be a global variable.
|
||
|
||
`(eq_attr NAME VALUE)'
|
||
NAME is a string specifying the name of an attribute.
|
||
|
||
VALUE is a string that is either a valid value for attribute NAME,
|
||
a comma-separated list of values, or `!' followed by a value or
|
||
list. If VALUE does not begin with a `!', this test is true if
|
||
the value of the NAME attribute of the current insn is in the list
|
||
specified by VALUE. If VALUE begins with a `!', this test is true
|
||
if the attribute's value is *not* in the specified list.
|
||
|
||
For example,
|
||
|
||
(eq_attr "type" "load,store")
|
||
|
||
is equivalent to
|
||
|
||
(ior (eq_attr "type" "load") (eq_attr "type" "store"))
|
||
|
||
If NAME specifies an attribute of `alternative', it refers to the
|
||
value of the compiler variable `which_alternative' (*note Output
|
||
Statement::.) and the values must be small integers. For example,
|
||
|
||
(eq_attr "alternative" "2,3")
|
||
|
||
is equivalent to
|
||
|
||
(ior (eq (symbol_ref "which_alternative") (const_int 2))
|
||
(eq (symbol_ref "which_alternative") (const_int 3)))
|
||
|
||
Note that, for most attributes, an `eq_attr' test is simplified in
|
||
cases where the value of the attribute being tested is known for
|
||
all insns matching a particular pattern. This is by far the most
|
||
common case.
|
||
|
||
|
||
File: gcc.info, Node: Tagging Insns, Next: Attr Example, Prev: Expressions, Up: Insn Attributes
|
||
|
||
Assigning Attribute Values to Insns
|
||
-----------------------------------
|
||
|
||
The value assigned to an attribute of an insn is primarily
|
||
determined by which pattern is matched by that insn (or which
|
||
`define_peephole' generated it). Every `define_insn' and
|
||
`define_peephole' can have an optional last argument to specify the
|
||
values of attributes for matching insns. The value of any attribute
|
||
not specified in a particular insn is set to the default value for that
|
||
attribute, as specified in its `define_attr'. Extensive use of default
|
||
values for attributes permits the specification of the values for only
|
||
one or two attributes in the definition of most insn patterns, as seen
|
||
in the example in the next section.
|
||
|
||
The optional last argument of `define_insn' and `define_peephole' is
|
||
a vector of expressions, each of which defines the value for a single
|
||
attribute. The most general way of assigning an attribute's value is
|
||
to use a `set' expression whose first operand is an `attr' expression
|
||
giving the name of the attribute being set. The second operand of the
|
||
`set' is an attribute expression (*note Expressions::.) giving the
|
||
value of the attribute.
|
||
|
||
When the attribute value depends on the `alternative' attribute
|
||
(i.e., which is the applicable alternative in the constraint of the
|
||
insn), the `set_attr_alternative' expression can can be used. It
|
||
allows the specification of a vector of attribute expressions, one for
|
||
each alternative.
|
||
|
||
When the generality of arbitrary attribute expressions is not
|
||
required, the simpler `set_attr' expression can be used, which allows
|
||
specifying a string giving either a single attribute value or a list of
|
||
attribute values, one for each alternative.
|
||
|
||
The form of each of the above specifications is shown below. In
|
||
each case, NAME is a string specifying the attribute to be set.
|
||
|
||
`(set_attr NAME VALUE-STRING)'
|
||
VALUE-STRING is either a string giving the desired attribute value,
|
||
or a string containing a comma-separated list giving the values for
|
||
succeeding alternatives. The number of elements must match the
|
||
number of alternatives in the constraint of the insn pattern.
|
||
|
||
Note that it may be useful to specify `*' for some alternative, in
|
||
which case the attribute will assume its default value for insns
|
||
matching that alternative.
|
||
|
||
`(set_attr_alternative NAME [VALUE1 VALUE2 ...])'
|
||
Depending on the alternative of the insn, the value will be one of
|
||
the specified values. This is a shorthand for using a `cond' with
|
||
tests on the `alternative' attribute.
|
||
|
||
`(set (attr NAME) VALUE)'
|
||
The first operand of this `set' must be the special RTL expression
|
||
`attr', whose sole operand is a string giving the name of the
|
||
attribute being set. VALUE is the value of the attribute.
|
||
|
||
The following shows three different ways of representing the same
|
||
attribute value specification:
|
||
|
||
(set_attr "type" "load,store,arith")
|
||
|
||
(set_attr_alternative "type"
|
||
[(const_string "load") (const_string "store")
|
||
(const_string "arith")])
|
||
|
||
(set (attr "type")
|
||
(cond [(eq_attr "alternative" "1") (const_string "load")
|
||
(eq_attr "alternative" "2") (const_string "store")]
|
||
(const_string "arith")))
|
||
|
||
The `define_asm_attributes' expression provides a mechanism to
|
||
specify the attributes assigned to insns produced from an `asm'
|
||
statement. It has the form:
|
||
|
||
(define_asm_attributes [ATTR-SETS])
|
||
|
||
where ATTR-SETS is specified the same as for `define_insn' and
|
||
`define_peephole' expressions.
|
||
|
||
These values will typically be the "worst case" attribute values.
|
||
For example, they might indicate that the condition code will be
|
||
clobbered.
|
||
|
||
A specification for a `length' attribute is handled specially. To
|
||
compute the length of an `asm' insn, the length specified in the
|
||
`define_asm_attributes' expression is multiplied by the number of
|
||
machine instructions specified in the `asm' statement, determined by
|
||
counting the number of semicolons and newlines in the string.
|
||
Therefore, the value of the `length' attribute specified in a
|
||
`define_asm_attributes' should be the maximum possible length of a
|
||
single machine instruction.
|
||
|
||
|
||
File: gcc.info, Node: Attr Example, Next: Insn Lengths, Prev: Tagging Insns, Up: Insn Attributes
|
||
|
||
Example of Attribute Specifications
|
||
-----------------------------------
|
||
|
||
The judicious use of defaulting is important in the efficient use of
|
||
insn attributes. Typically, insns are divided into "types" and an
|
||
attribute, customarily called `type', is used to represent this value.
|
||
This attribute is normally used only to define the default value for
|
||
other attributes. An example will clarify this usage.
|
||
|
||
Assume we have a RISC machine with a condition code and in which only
|
||
full-word operations are performed in registers. Let us assume that we
|
||
can divide all insns into loads, stores, (integer) arithmetic
|
||
operations, floating point operations, and branches.
|
||
|
||
Here we will concern ourselves with determining the effect of an
|
||
insn on the condition code and will limit ourselves to the following
|
||
possible effects: The condition code can be set unpredictably
|
||
(clobbered), not be changed, be set to agree with the results of the
|
||
operation, or only changed if the item previously set into the
|
||
condition code has been modified.
|
||
|
||
Here is part of a sample `md' file for such a machine:
|
||
|
||
(define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
|
||
|
||
(define_attr "cc" "clobber,unchanged,set,change0"
|
||
(cond [(eq_attr "type" "load")
|
||
(const_string "change0")
|
||
(eq_attr "type" "store,branch")
|
||
(const_string "unchanged")
|
||
(eq_attr "type" "arith")
|
||
(if_then_else (match_operand:SI 0 "" "")
|
||
(const_string "set")
|
||
(const_string "clobber"))]
|
||
(const_string "clobber")))
|
||
|
||
(define_insn ""
|
||
[(set (match_operand:SI 0 "general_operand" "=r,r,m")
|
||
(match_operand:SI 1 "general_operand" "r,m,r"))]
|
||
""
|
||
"@
|
||
move %0,%1
|
||
load %0,%1
|
||
store %0,%1"
|
||
[(set_attr "type" "arith,load,store")])
|
||
|
||
Note that we assume in the above example that arithmetic operations
|
||
performed on quantities smaller than a machine word clobber the
|
||
condition code since they will set the condition code to a value
|
||
corresponding to the full-word result.
|
||
|
||
|
||
File: gcc.info, Node: Insn Lengths, Next: Constant Attributes, Prev: Attr Example, Up: Insn Attributes
|
||
|
||
Computing the Length of an Insn
|
||
-------------------------------
|
||
|
||
For many machines, multiple types of branch instructions are
|
||
provided, each for different length branch displacements. In most
|
||
cases, the assembler will choose the correct instruction to use.
|
||
However, when the assembler cannot do so, GCC can when a special
|
||
attribute, the `length' attribute, is defined. This attribute must be
|
||
defined to have numeric values by specifying a null string in its
|
||
`define_attr'.
|
||
|
||
In the case of the `length' attribute, two additional forms of
|
||
arithmetic terms are allowed in test expressions:
|
||
|
||
`(match_dup N)'
|
||
This refers to the address of operand N of the current insn, which
|
||
must be a `label_ref'.
|
||
|
||
`(pc)'
|
||
This refers to the address of the *current* insn. It might have
|
||
been more consistent with other usage to make this the address of
|
||
the *next* insn but this would be confusing because the length of
|
||
the current insn is to be computed.
|
||
|
||
For normal insns, the length will be determined by value of the
|
||
`length' attribute. In the case of `addr_vec' and `addr_diff_vec' insn
|
||
patterns, the length will be computed as the number of vectors
|
||
multiplied by the size of each vector.
|
||
|
||
The following macros can be used to refine the length computation:
|
||
|
||
`FIRST_INSN_ADDRESS'
|
||
When the `length' insn attribute is used, this macro specifies the
|
||
value to be assigned to the address of the first insn in a
|
||
function. If not specified, 0 is used.
|
||
|
||
`ADJUST_INSN_LENGTH (INSN, LENGTH)'
|
||
If defined, modifies the length assigned to instruction INSN as a
|
||
function of the context in which it is used. LENGTH is an lvalue
|
||
that contains the initially computed length of the insn and should
|
||
be updated with the correct length of the insn. If updating is
|
||
required, INSN must not be a varying-length insn.
|
||
|
||
This macro will normally not be required. A case in which it is
|
||
required is the ROMP. On this machine, the size of an `addr_vec'
|
||
insn must be increased by two to compensate for the fact that
|
||
alignment may be required.
|
||
|
||
The routine that returns the value of the `length' attribute,
|
||
`get_attr_length', can be used by the output routine to determine the
|
||
form of the branch instruction to be written, as the example below
|
||
illustrates.
|
||
|
||
As an example of the specification of variable-length branches,
|
||
consider the IBM 360. If we adopt the convention that a register will
|
||
be set to the starting address of a function, we can jump to labels
|
||
within 4K of the start using a four-byte instruction. Otherwise, we
|
||
need a six-byte sequence to load the address from memory and then
|
||
branch to it.
|
||
|
||
On such a machine, a pattern for a branch instruction might be
|
||
specified as follows:
|
||
|
||
(define_insn "jump"
|
||
[(set (pc)
|
||
(label_ref (match_operand 0 "" "")))]
|
||
""
|
||
"*
|
||
{
|
||
return (get_attr_length (insn) == 4
|
||
? \"b %l0\" : \"l r15,=a(%l0); br r15\");
|
||
}"
|
||
[(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
|
||
(const_int 4)
|
||
(const_int 6)))])
|
||
|
||
|
||
File: gcc.info, Node: Constant Attributes, Next: Delay Slots, Prev: Insn Lengths, Up: Insn Attributes
|
||
|
||
Constant Attributes
|
||
-------------------
|
||
|
||
A special form of `define_attr', where the expression for the
|
||
default value is a `const' expression, indicates an attribute that is
|
||
constant for a given run of the compiler. Constant attributes may be
|
||
used to specify which variety of processor is used. For example,
|
||
|
||
(define_attr "cpu" "m88100,m88110,m88000"
|
||
(const
|
||
(cond [(symbol_ref "TARGET_88100") (const_string "m88100")
|
||
(symbol_ref "TARGET_88110") (const_string "m88110")]
|
||
(const_string "m88000"))))
|
||
|
||
(define_attr "memory" "fast,slow"
|
||
(const
|
||
(if_then_else (symbol_ref "TARGET_FAST_MEM")
|
||
(const_string "fast")
|
||
(const_string "slow"))))
|
||
|
||
The routine generated for constant attributes has no parameters as it
|
||
does not depend on any particular insn. RTL expressions used to define
|
||
the value of a constant attribute may use the `symbol_ref' form, but
|
||
may not use either the `match_operand' form or `eq_attr' forms
|
||
involving insn attributes.
|
||
|
||
|
||
File: gcc.info, Node: Delay Slots, Next: Function Units, Prev: Constant Attributes, Up: Insn Attributes
|
||
|
||
Delay Slot Scheduling
|
||
---------------------
|
||
|
||
The insn attribute mechanism can be used to specify the requirements
|
||
for delay slots, if any, on a target machine. An instruction is said to
|
||
require a "delay slot" if some instructions that are physically after
|
||
the instruction are executed as if they were located before it. Classic
|
||
examples are branch and call instructions, which often execute the
|
||
following instruction before the branch or call is performed.
|
||
|
||
On some machines, conditional branch instructions can optionally
|
||
"annul" instructions in the delay slot. This means that the
|
||
instruction will not be executed for certain branch outcomes. Both
|
||
instructions that annul if the branch is true and instructions that
|
||
annul if the branch is false are supported.
|
||
|
||
Delay slot scheduling differs from instruction scheduling in that
|
||
determining whether an instruction needs a delay slot is dependent only
|
||
on the type of instruction being generated, not on data flow between the
|
||
instructions. See the next section for a discussion of data-dependent
|
||
instruction scheduling.
|
||
|
||
The requirement of an insn needing one or more delay slots is
|
||
indicated via the `define_delay' expression. It has the following form:
|
||
|
||
(define_delay TEST
|
||
[DELAY-1 ANNUL-TRUE-1 ANNUL-FALSE-1
|
||
DELAY-2 ANNUL-TRUE-2 ANNUL-FALSE-2
|
||
...])
|
||
|
||
TEST is an attribute test that indicates whether this `define_delay'
|
||
applies to a particular insn. If so, the number of required delay
|
||
slots is determined by the length of the vector specified as the second
|
||
argument. An insn placed in delay slot N must satisfy attribute test
|
||
DELAY-N. ANNUL-TRUE-N is an attribute test that specifies which insns
|
||
may be annulled if the branch is true. Similarly, ANNUL-FALSE-N
|
||
specifies which insns in the delay slot may be annulled if the branch
|
||
is false. If annulling is not supported for that delay slot, `(nil)'
|
||
should be coded.
|
||
|
||
For example, in the common case where branch and call insns require
|
||
a single delay slot, which may contain any insn other than a branch or
|
||
call, the following would be placed in the `md' file:
|
||
|
||
(define_delay (eq_attr "type" "branch,call")
|
||
[(eq_attr "type" "!branch,call") (nil) (nil)])
|
||
|
||
Multiple `define_delay' expressions may be specified. In this case,
|
||
each such expression specifies different delay slot requirements and
|
||
there must be no insn for which tests in two `define_delay' expressions
|
||
are both true.
|
||
|
||
For example, if we have a machine that requires one delay slot for
|
||
branches but two for calls, no delay slot can contain a branch or call
|
||
insn, and any valid insn in the delay slot for the branch can be
|
||
annulled if the branch is true, we might represent this as follows:
|
||
|
||
(define_delay (eq_attr "type" "branch")
|
||
[(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)])
|
||
|
||
(define_delay (eq_attr "type" "call")
|
||
[(eq_attr "type" "!branch,call") (nil) (nil)
|
||
(eq_attr "type" "!branch,call") (nil) (nil)])
|
||
|
||
|
||
File: gcc.info, Node: Function Units, Prev: Delay Slots, Up: Insn Attributes
|
||
|
||
Specifying Function Units
|
||
-------------------------
|
||
|
||
On most RISC machines, there are instructions whose results are not
|
||
available for a specific number of cycles. Common cases are
|
||
instructions that load data from memory. On many machines, a pipeline
|
||
stall will result if the data is referenced too soon after the load
|
||
instruction.
|
||
|
||
In addition, many newer microprocessors have multiple function
|
||
units, usually one for integer and one for floating point, and often
|
||
will incur pipeline stalls when a result that is needed is not yet
|
||
ready.
|
||
|
||
The descriptions in this section allow the specification of how much
|
||
time must elapse between the execution of an instruction and the time
|
||
when its result is used. It also allows specification of when the
|
||
execution of an instruction will delay execution of similar instructions
|
||
due to function unit conflicts.
|
||
|
||
For the purposes of the specifications in this section, a machine is
|
||
divided into "function units", each of which execute a specific class
|
||
of instructions. Function units that accept one instruction each cycle
|
||
and allow a result to be used in the succeeding instruction (usually
|
||
via forwarding) need not be specified. Classic RISC microprocessors
|
||
will normally have a single function unit, which we can call `memory'.
|
||
The newer "superscalar" processors will often have function units for
|
||
floating point operations, usually at least a floating point adder and
|
||
multiplier.
|
||
|
||
Each usage of a function units by a class of insns is specified with
|
||
a `define_function_unit' expression, which looks like this:
|
||
|
||
(define_function_unit NAME MULTIPLICITY SIMULTANEITY
|
||
TEST READY-DELAY BUSY-DELAY
|
||
[CONFLICT-LIST])
|
||
|
||
NAME is a string giving the name of the function unit.
|
||
|
||
MULTIPLICITY is an integer specifying the number of identical units
|
||
in the processor. If more than one unit is specified, they will be
|
||
scheduled independently. Only truly independent units should be
|
||
counted; a pipelined unit should be specified as a single unit. (The
|
||
only common example of a machine that has multiple function units for a
|
||
single instruction class that are truly independent and not pipelined
|
||
are the two multiply and two increment units of the CDC 6600.)
|
||
|
||
SIMULTANEITY specifies the maximum number of insns that can be
|
||
executing in each instance of the function unit simultaneously or zero
|
||
if the unit is pipelined and has no limit.
|
||
|
||
All `define_function_unit' definitions referring to function unit
|
||
NAME must have the same name and values for MULTIPLICITY and
|
||
SIMULTANEITY.
|
||
|
||
TEST is an attribute test that selects the insns we are describing
|
||
in this definition. Note that an insn may use more than one function
|
||
unit and a function unit may be specified in more than one
|
||
`define_function_unit'.
|
||
|
||
READY-DELAY is an integer that specifies the number of cycles after
|
||
which the result of the instruction can be used without introducing any
|
||
stalls.
|
||
|
||
BUSY-DELAY is an integer that represents the default cost if an insn
|
||
is scheduled for this unit while the unit is active with another insn.
|
||
If SIMULTANEITY is zero, this specification is ignored. Otherwise, a
|
||
zero value indicates that these insns execute on NAME in a fully
|
||
pipelined fashion, even if SIMULTANEITY is non-zero. A non-zero value
|
||
indicates that scheduling a new insn on this unit while another is
|
||
active will incur a cost. A cost of two indicates a single cycle
|
||
delay. For a normal non-pipelined function unit, BUSY-DELAY will be
|
||
twice READY-DELAY.
|
||
|
||
CONFLICT-LIST is an optional list giving detailed conflict costs for
|
||
this unit. If specified, it is a list of condition test expressions
|
||
which are applied to insns already executing in NAME. For each insn
|
||
that is in the list, BUSY-DELAY will be used for the conflict cost,
|
||
while a value of zero will be used for insns not in the list.
|
||
|
||
Typical uses of this vector are where a floating point function unit
|
||
can pipeline either single- or double-precision operations, but not
|
||
both, or where a memory unit can pipeline loads, but not stores, etc.
|
||
|
||
As an example, consider a classic RISC machine where the result of a
|
||
load instruction is not available for two cycles (a single "delay"
|
||
instruction is required) and where only one load instruction can be
|
||
executed simultaneously. This would be specified as:
|
||
|
||
(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 4)
|
||
|
||
For the case of a floating point function unit that can pipeline
|
||
either single or double precision, but not both, the following could be
|
||
specified:
|
||
|
||
(define_function_unit
|
||
"fp" 1 1 (eq_attr "type" "sp_fp") 4 8 (eq_attr "type" "dp_fp")]
|
||
(define_function_unit
|
||
"fp" 1 1 (eq_attr "type" "dp_fp") 4 8 (eq_attr "type" "sp_fp")]
|
||
|
||
*Note:* No code currently exists to avoid function unit conflicts,
|
||
only data conflicts. Hence MULTIPLICITY, SIMULTANEITY, BUSY-COST, and
|
||
CONFLICT-LIST are currently ignored. When such code is written, it is
|
||
possible that the specifications for these values may be changed. It
|
||
has recently come to our attention that these specifications may not
|
||
allow modeling of some of the newer "superscalar" processors that have
|
||
insns using multiple pipelined units. These insns will cause a
|
||
potential conflict for the second unit used during their execution and
|
||
there is no way of representing that conflict. We welcome any examples
|
||
of how function unit conflicts work in such processors and suggestions
|
||
for their representation.
|
||
|
||
|
||
File: gcc.info, Node: Target Macros, Next: Config, Prev: Machine Desc, Up: Top
|
||
|
||
Target Description Macros
|
||
*************************
|
||
|
||
In addition to the file `MACHINE.md', a machine description includes
|
||
a C header file conventionally given the name `MACHINE.h'. This header
|
||
file defines numerous macros that convey the information about the
|
||
target machine that does not fit into the scheme of the `.md' file.
|
||
The file `tm.h' should be a link to `MACHINE.h'. The header file
|
||
`config.h' includes `tm.h' and most compiler source files include
|
||
`config.h'.
|
||
|
||
* Menu:
|
||
|
||
* Driver:: Controlling how the driver runs the compilation passes.
|
||
* Run-time Target:: Defining `-m' options like `-m68000' and `-m68020'.
|
||
* Storage Layout:: Defining sizes and alignments of data.
|
||
* Type Layout:: Defining sizes and properties of basic user data types.
|
||
* Registers:: Naming and describing the hardware registers.
|
||
* Register Classes:: Defining the classes of hardware registers.
|
||
* Stack and Calling:: Defining which way the stack grows and by how much.
|
||
* Varargs:: Defining the varargs macros.
|
||
* Trampolines:: Code set up at run time to enter a nested function.
|
||
* Library Calls:: Controlling how library routines are implicitly called.
|
||
* Addressing Modes:: Defining addressing modes valid for memory operands.
|
||
* Condition Code:: Defining how insns update the condition code.
|
||
* Costs:: Defining relative costs of different operations.
|
||
* Sections:: Dividing storage into text, data, and other sections.
|
||
* PIC:: Macros for position independent code.
|
||
* Assembler Format:: Defining how to write insns and pseudo-ops to output.
|
||
* Debugging Info:: Defining the format of debugging output.
|
||
* Cross-compilation:: Handling floating point for cross-compilers.
|
||
* Misc:: Everything else.
|
||
|
||
|