69 lines
3.8 KiB
HTML
69 lines
3.8 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<html>
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<head>
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<title>80386 Programmer's Reference Manual -- Opcode BTR</title>
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</head>
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<body>
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<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a><br>
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<b>next:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a>
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<p>
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<hr>
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<p>
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<h1>BTR -- Bit Test and Reset</h1>
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<pre>
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Opcode Instruction Clocks Description
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0F B3 BTR r/m16,r16 6/13 Save bit in carry flag and reset
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0F B3 BTR r/m32,r32 6/13 Save bit in carry flag and reset
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0F BA /6 ib BTR r/m16,imm8 6/8 Save bit in carry flag and reset
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0F BA /6 ib BTR r/m32,imm8 6/8 Save bit in carry flag and reset
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</pre>
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<h2>Operation</h2>
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<pre>
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CF := BIT[LeftSRC, RightSRC];
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BIT[LeftSRC, RightSRC] := 0;
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</pre>
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<h2>Description</h2>
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BTR saves the value of the bit indicated by the base (first operand) and the bit offset (second operand) into the carry flag and then stores 0 in the bit.
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<h2>Flags Affected</h2>
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CF as described above
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<h2>Protected Mode Exceptions</h2>
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#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
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<h2>Real Address Mode Exceptions</h2>
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Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
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<h2>Virtual 8086 Mode Exceptions</h2>
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Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
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<h2>Notes</h2>
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The index of the selected bit can be given by the immediate constant in the instruction or by a value in a general register. Only an 8-bit immediate value is used in the instruction. This operand is taken modulo 32, so the range of immediate bit offsets is 0..31. This allows any bit within a register to be selected. For memory bit strings, this immediate field gives only the bit offset within a word or doubleword. Immediate bit offsets larger than 31 (or 15) are supported by using the immediate bit offset field in combination with the displacement field of the memory operand. The low-order 3 to 5 bits of the immediate bit offset are stored in the immediate bit offset field, and the high-order 27 to 29 bits are shifted and combined with the byte displacement in the addressing mode.
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<p>When accessing a bit in memory, the 80386 may access four bytes starting from the memory address given by:
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<pre>
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Effective Address + 4 * (BitOffset DIV 32)
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</pre>
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for a 32-bit operand size, or two bytes starting from the memory address given by:
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<pre>
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Effective Address + 2 * (BitOffset DIV 16)
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</pre>
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for a 16-bit operand size. It may do so even when only a single byte needs to be accessed in order to reach the given bit. You must therefore avoid referencing areas of memory close to address space holes. In particular, avoid references to memory-mapped I/O registers. Instead, use the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the data.
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<p>
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<hr>
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<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM"> BTC Bit Test and Complement</a><br>
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<b>next:</b><a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM"> BTS Bit Test and Set</a>
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</body>
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