27 lines
2.3 KiB
HTML
27 lines
2.3 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Chapter 12</title>
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<body>
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<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
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<b>prev:</b> <a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a><br>
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<b>next:</b> <a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a>
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<p>
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<hr>
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<p>
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<h1>Chapter 12 Debugging</h1>
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<p>The 80386 brings to Intel's line of microprocessors significant advances in debugging power. The single-step exception and breakpoint exception of previous processors are still available in the 80386, but the principal debugging support takes the form of debug registers. The debug registers support both instruction breakpoints and data breakpoints. Data breakpoints are an important innovation that can save hours of debugging time by pinpointing, for example, exactly when a data structure is being overwritten. The breakpoint registers also eliminate the complexities associated with writing a breakpoint instruction into a code segment (requires a data-segment alias for the code segment) or a code segment shared by multiple tasks (the breakpoint exception can occur in the context of any of the tasks). Breakpoints can even be set in code contained in ROM.
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<p><a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a><br>
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<a href="S12_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_02.HTM">12.2 Debug Registers</a><br>
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<a href="S12_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_03.HTM">12.3 Debug Exceptions</a>
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<p>
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<hr>
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<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
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<b>prev:</b> <a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a><br>
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<b>next:</b> <a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a>
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</body>
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