64 lines
3.9 KiB
HTML
64 lines
3.9 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<html>
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<head>
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<title>80386 Programmer's Reference Manual -- Opcode LGDT</title>
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</head>
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<body>
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<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM"> LEAVE High Level Procedure Exit</a><br>
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<b>next:</b><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM"> LGS/LSS/LDS/LES/LFS Load Full Pointer</a>
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<p>
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<hr>
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<p>
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<h1>LGDT/LIDT -- Load Global/Interrupt Descriptor Table Register</h1>
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<pre>
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Opcode Instruction Clocks Description
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0F 01 /2 LGDT m16&32 11 Load m into GDTR
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0F 01 /3 LIDT m16&32 11 Load m into IDTR
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</pre>
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<h2>Operation</h2>
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<pre>
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IF instruction = LIDT
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THEN
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IF OperandSize = 16
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THEN IDTR.Limit:Base := m16:24 (* 24 bits of base loaded *)
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ELSE IDTR.Limit:Base := m16:32
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FI;
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ELSE (* instruction = LGDT *)
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IF OperandSize = 16
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THEN GDTR.Limit:Base := m16:24 (* 24 bits of base loaded *)
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ELSE GDTR.Limit:Base := m16:32;
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FI;
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FI;
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</pre>
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<h2>Description</h2>
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The LGDT and LIDT instructions load a linear base address and limit value from a six-byte data operand in memory into the GDTR or IDTR, respectively. If a 16-bit operand is used with LGDT or LIDT, the register is loaded with a 16-bit limit and a 24-bit base, and the high-order eight bits of the six-byte data operand are not used. If a 32-bit operand is used, a 16-bit limit and a 32-bit base is loaded; the high-order eight bits of the six-byte operand are used as high-order base address bits.
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<p>The <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SGDT</a> and <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> instructions always store into all 48 bits of the six-byte data operand. With the 80286, the upper eight bits are undefined after <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SGDT</a> or <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> is executed. With the 80386, the upper eight bits are written with the high-order eight address bits, for both a 16-bit operand and a 32-bit operand. If LGDT or LIDT is used with a 16-bit operand to load the register stored by SGDT or SIDT, the upper eight bits are stored as zeros.
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<p>LGDT and LIDT appear in operating system software; they are not used in application programs. They are the only instructions that directly load a linear address (i.e., not a segment relative address) in 80386 Protected Mode.
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<h2>Flags Affected</h2>
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None
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<h2>Protected Mode Exceptions</h2>
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#GP(0) if the current privilege level is not 0; #UD if the source operand is a register; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
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<h2>Real Address Mode Exceptions</h2>
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Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH; Interrupt 6 if the source operand is a register <em>
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<h3>Note</h3>
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These instructions are valid in Real Address Mode to allow power-up initialization for Protected Mode </em>
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<h2>Virtual 8086 Mode Exceptions</h2>
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Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault
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<p>
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<hr>
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<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM"> LEAVE High Level Procedure Exit</a><br>
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<b>next:</b><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM"> LGS/LSS/LDS/LES/LFS Load Full Pointer</a>
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</body>
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