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103 lines
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<title>80386 Programmer's Reference Manual -- Section 3.5</title>
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<body>
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<b>up:</b> <a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">Chapter 3 -- Applications Instruction Set</a><br>
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<b>prev:</b> <a href="S03_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_04.HTM">3.4 Logical Instructions</a><br>
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<b>next:</b> <a href="S03_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_06.HTM">3.6 String and Character Translation Instructions</a>
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<p>
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<p>
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<h1>3.5 Control Transfer Instructions</h1>
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The 80386 provides both conditional and unconditional control transfer instructions to direct the flow of execution. Conditional control transfers depend on the results of operations that affect the flag register. Unconditional control transfers are always executed.
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<h2>3.5.1 Unconditional Transfer Instructions</h2>
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<a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>, <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a>, <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a>, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> and <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instructions transfer control from one code segment location to another. These locations can be within the same code segment (near control transfers) or in different code segments (far control transfers). The variants of these instructions that transfer control to other segments are discussed in a later section of this chapter. If the model of memory organization used in a particular 80386 application does not make segments visible to applications programmers, intersegment control transfers will not be used.
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<h3>3.5.1.1 Jump Instruction</h3>
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<a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> (Jump) unconditionally transfers control to the target location. <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> is a one-way transfer of execution; it does not save a return address on the stack.
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<p>The <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instruction always performs the same basic function of transferring control from the current location to a new location. Its implementation varies depending on whether the address is specified directly within the instruction or indirectly through a register or memory.
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<p>A direct <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instruction includes the destination address as part of the instruction. An indirect <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instruction obtains the destination address indirectly through a register or a pointer variable.
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<p>Direct near <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>. A direct <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> uses a relative displacement value contained in the instruction. The displacement is signed and the size of the displacement may be a byte, word, or doubleword. The processor forms an effective address by adding this relative displacement to the address contained in EIP. When the additions have been performed, EIP refers to the next instruction to be executed.
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<p>Indirect near <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>. Indirect <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instructions specify an absolute address in one of several ways:
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<ol>
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<li>The program can <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> to a location specified by a general register (any of EAX, EDX, ECX, EBX, EBP, ESI, or EDI). The processor moves this 32-bit value into EIP and resumes execution.
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<li>The processor can obtain the destination address from a memory operand specified in the instruction.
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<li>A register can modify the address of the memory pointer to select a destination address.
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</ol>
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<h3>3.5.1.2 Call Instruction</h3>
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<a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> (Call Procedure) activates an out-of-line procedure, saving on the stack the address of the instruction following the <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> for later use by a <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> (Return) instruction. <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> places the current value of EIP on the stack. The <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> instruction in the called procedure uses this address to transfer control back to the calling program.
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<p><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instructions, like <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instructions have relative, direct, and indirect versions.
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<p>Indirect <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instructions specify an absolute address in one of these ways:
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<ol>
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<li>The program can <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> a location specified by a general register (any of EAX, EDX, ECX, EBX, EBP, ESI, or EDI). The processor moves this 32-bit value into EIP.
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<li>The processor can obtain the destination address from a memory operand specified in the instruction.
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</ol>
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<h3>3.5.1.3 Return and Return-From-Interrupt Instruction</h3>
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<a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> (Return From Procedure) terminates the execution of a procedure and transfers control through a back-link on the stack to the program that originally invoked the procedure. <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> restores the value of EIP that was saved on the stack by the previous <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instruction.
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<p><a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> instructions may optionally specify an immediate operand. By adding this constant to the new top-of-stack pointer, <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> effectively removes any arguments that the calling program pushed on the stack before the execution of the <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instruction.
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<p><a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> (Return From Interrupt) returns control to an interrupted procedure. <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> differs from <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> in that it also pops the flags from the stack into the flags register. The flags are stored on the stack by the interrupt mechanism.
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<h2>3.5.2 Conditional Transfer Instructions</h2>
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The conditional transfer instructions are jumps that may or may not transfer control, depending on the state of the CPU flags when the instruction executes.
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<h3>3.5.2.1 Conditional Jump Instructions</h3>
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Table 3-2 shows the conditional transfer mnemonics and their interpretations. The conditional jumps that are listed as pairs are actually the same instruction. The assembler provides the alternate mnemonics for greater clarity within a program listing.
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<p>Conditional jump instructions contain a displacement which is added to the EIP register if the condition is true. The displacement may be a byte, a word, or a doubleword. The displacement is signed; therefore, it can be used to jump forward or backward.
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<pre>
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Table 3-2. Interpretation of Conditional Transfers
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Unsigned Conditional Transfers
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Mnemonic Condition Tested "Jump If..."
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JA/JNBE (CF or ZF) = 0 above/not below nor equal
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JAE/JNB CF = 0 above or equal/not below
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JB/JNAE CF = 1 below/not above nor equal
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JBE/JNA (CF or ZF) = 1 below or equal/not above
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JC CF = 1 carry
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JE/JZ ZF = 1 equal/zero
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JNC CF = 0 not carry
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JNE/JNZ ZF = 0 not equal/not zero
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JNP/JPO PF = 0 not parity/parity odd
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JP/JPE PF = 1 parity/parity even
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Signed Conditional Transfers
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Mnemonic Condition Tested "Jump If..."
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JG/JNLE ((SF xor OF) or ZF) = 0 greater/not less nor equal
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JGE/JNL (SF xor OF) = 0 greater or equal/not less
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JL/JNGE (SF xor OF) = 1 less/not greater nor equal
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JLE/JNG ((SF xor OF) or ZF) = 1 less or equal/not greater
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JNO OF = 0 not overflow
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JNS SF = 0 not sign (positive, including 0)
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JO OF = 1 overflow
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JS SF = 1 sign (negative)
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</pre>
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<h3>3.5.2.2 Loop Instructions</h3>
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The loop instructions are conditional jumps that use a value placed in ECX to specify the number of repetitions of a software loop. All loop instructions automatically decrement ECX and terminate the loop when ECX=0. Four of the five loop instructions specify a condition involving ZF that terminates the loop before ECX reaches zero.
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<p><a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> (Loop While ECX Not Zero) is a conditional transfer that automatically decrements the ECX register before testing ECX for the branch condition. If ECX is non-zero, the program branches to the target label specified in the instruction. The <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> instruction causes the repetition of a code section until the operation of the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> instruction decrements ECX to a value of zero. If <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> finds ECX=0, control transfers to the instruction immediately following the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> instruction. If the value of ECX is initially zero, then the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> executes 2^(32) times.
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<p><a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPE</a> (Loop While Equal) and <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPZ</a> (Loop While Zero) are synonyms for the same instruction. These instructions automatically decrement the ECX register before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=1, the program branches to the target label specified in the instruction. If <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPE</a> or <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPZ</a> finds that ECX=0 or ZF=0, control transfers to the instruction immediately following the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPE</a> or <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPZ</a> instruction.
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<p><a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNE</a> (Loop While Not Equal) and <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNZ</a> (Loop While Not Zero) are synonyms for the same instruction. These instructions automatically decrement the ECX register before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=0, the program branches to the target label specified in the instruction. If <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNE</a> or <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNZ</a> finds that ECX=0 or ZF=1, control transfers to the instruction immediately following the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNE</a> or <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOPNZ</a> instruction.
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<h3>3.5.2.3 Executing a Loop or Repeat Zero Times</h3>
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<a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a> (Jump if ECX Zero) branches to the label specified in the instruction if it finds a value of zero in ECX. <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a> is useful in combination with the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> instruction and with the string scan and compare instructions, all of which decrement ECX. Sometimes, it is desirable to design a loop that executes zero times if the count variable in ECX is initialized to zero. Because the <a href="LOOP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOOP.HTM">LOOP</a> instructions (and repeat prefixes) decrement ECX before they test it, a loop will execute 2^(32) times if the program enters the loop with a zero value in ECX. A programmer may conveniently overcome this problem with <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a>, which enables the program to branch around the code within the loop if ECX is zero when <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a> executes. When used with repeated string scan and compare instructions, <a href="JCC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JCC.HTM">JCXZ</a> can determine whether the repetitions terminated due to zero in ECX or due to satisfaction of the scan or compare conditions.
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<h2>3.5.3 Software-Generated Interrupts</h2>
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The <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a>, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM" into<></a>, and <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> instructions allow the programmer to specify a transfer to an interrupt service routine from within a program.
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<p><a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a> (Software Interrupt) activates the interrupt service routine that corresponds to the number coded within the instruction. The <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> instruction may specify any interrupt type. Programmers may use this flexibility to implement multiple types of internal interrupts or to test the operation of interrupt service routines. (Interrupts 0-31 are reserved by Intel.) The interrupt service routine terminates with an <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instruction that returns control to the instruction that follows <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a>.
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<p><a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INTO</a> (Interrupt on Overflow) invokes interrupt 4 if OF is set. Interrupt 4 is reserved for this purpose. OF is set by several arithmetic, logical, and string instructions.
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<p><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> (Detect Value Out of Range) verifies that the signed value contained in the specified register lies within specified limits. An interrupt (<a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> 5) occurs if the value contained in the register is less than the lower bound or greater than the upper bound.
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<p>The <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> instruction includes two operands. The first operand specifies the register being tested. The second operand contains the effective relative address of the two signed <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> limit values. The <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> instruction assumes that the upper limit and lower limit are in adjacent memory locations. These limit values cannot be register operands; if they are, an invalid opcode exception occurs.
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<p><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> is useful for checking array bounds before using a new index value to access an element within the array. <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> provides a simple way to check the value of an index register before the program overwrites information in a location beyond the limit of the array.
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<p>The block of memory that specifies the lower and upper limits of an array might typically reside just before the array itself. This makes the array bounds accessible at a constant offset from the beginning of the array. Because the address of the array will already be present in a register, this practice avoids extra calculations to obtain the effective address of the array bounds.
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<p>The upper and lower limit values may each be a word or a doubleword.
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<p>
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<hr>
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<p><b>up:</b> <a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">Chapter 3 -- Applications Instruction Set</a><br>
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<b>prev:</b> <a href="S03_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_04.HTM">3.4 Logical Instructions</a><br>
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<b>next:</b> <a href="S03_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_06.HTM">3.6 String and Character Translation Instructions</a>
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</body>
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