49 lines
3.5 KiB
HTML
49 lines
3.5 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 7.1</title>
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</head>
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<body>
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<b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>prev:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>next:</b> <a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a>
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<p>
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<hr>
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<p>
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<h1>7.1 Task State Segment</h1>
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All the information the processor needs in order to manage a task is stored in a special type of segment, a task state segment (TSS). <a href="#fig7-1">Figure 7-1</a> shows the format of a TSS for executing 80386 tasks. (Another format is used for executing 80286 tasks; refer to <a href="C13.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C13.HTM">Chapter 13</a>.)
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<p>The fields of a TSS belong to two classes:
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<ol>
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<li>A dynamic set that the processor updates with each switch from the task. This set includes the fields that store:
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<ul>
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<li>The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
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<li>The segment registers (ES, CS, SS, DS, FS, GS).
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<li>The flags register (EFLAGS).
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<li>The instruction pointer (EIP).
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<li>The selector of the TSS of the previously executing task (updated only when a return is expected).
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</ul>
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<li>A static set that the processor reads but does not change. This set includes the fields that store:
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<ul>
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<li>The selector of the task's LDT.
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<li>The register (PDBR) that contains the base address of the task's page directory (read only when paging is enabled).
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<li>Pointers to the stacks for privilege levels 0-2.
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<li>The T-bit (debug trap bit) which causes the processor to raise a debug exception when a task switch occurs . (Refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> for more information on debugging.)
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<li>The I/O map base (refer to <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8</a> for more information on the use of the I/O map).
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</ul>
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</ol>
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Task state segments may reside anywhere in the linear space. The only case that requires caution is when the TSS spans a page boundary and the higher-addressed page is not present. In this case, the processor raises an exception if it encounters the not-present page while reading the TSS during a task switch. Such an exception can be avoided by either of two strategies:
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<ol>
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<li>By allocating the TSS so that it does not cross a page boundary.
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<li>By ensuring that both pages are either both present or both not-present at the time of a task switch. If both pages are not-present, then the page-fault handler must make both pages present before restarting the instruction that caused the task switch.
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</ol>
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<a name="fig7-1"><img align="center" src="FIG7-1.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG7-1.GIF" border="0">
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<p>
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<hr>
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<p><b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>prev:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>next:</b> <a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a>
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</body>
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