49 lines
5.1 KiB
HTML
49 lines
5.1 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 9.2</title>
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<b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
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<b>prev:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a><br>
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<b>next:</b> <a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a>
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<p>
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<h1>9.2 Enabling and Disabling Interrupts</h1>
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The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next. When the repeat prefix is used to repeat a string instruction, interrupts and exceptions may occur between repetitions. Thus, operations on long strings do not delay interrupt response.
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<p>Certain conditions and flag settings cause the processor to inhibit certain interrupts and exceptions at instruction boundaries.
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<h2>9.2.1 NMI Masks Further NMIs</h2>
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While an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instruction is executed.
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<h2>9.2.2 IF Masks INTR</h2>
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The IF (interrupt-enable flag) controls the acceptance of external interrupts signalled via the INTR pin. When IF=0, INTR interrupts are inhibited; when IF=1, INTR interrupts are enabled. As with the other flag bits, the processor clears IF in response to a RESET signal. The instructions <a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI</a> and <a href="STI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STI.HTM">STI</a> alter the setting of IF.
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<p><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI</a> (Clear Interrupt-Enable Flag) and <a href="STI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STI.HTM">STI</a> (Set Interrupt-Enable Flag) explicitly alter IF (bit 9 in the flag register). These instructions may be executed only if CPL <= IOPL. A protection exception occurs if they are executed when CPL > IOPL.
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<p>The IF is also affected implicitly by the following operations:
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<ul>
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<li>The instruction <a href="PUSHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHF.HTM">PUSHF</a> stores all flags, including IF, in the stack where they can be examined.
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<li>Task switches and the instructions <a href="POPF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPF.HTM">POPF</a> and <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> load the flags register; therefore, they can be used to modify IF.
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<li>Interrupts through interrupt gates automatically reset IF, disabling interrupts. (Interrupt gates are explained later in this chapter.)
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</ul>
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<h2>9.2.3 RF Masks Debug Faults</h2>
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The RF bit in EFLAGS controls the recognition of debug faults. This permits debug faults to be raised for a given instruction at most once, no matter how many times the instruction is restarted . (Refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> for more information on debugging.)
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<h2>9.2.4 MOV or POP to SS Masks Some Interrupts and Exceptions</h2>
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Software that needs to change stack segments often uses a pair of instructions; for example:
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<pre>
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<a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> SS, AX
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<a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> ESP, StackTop
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</pre>
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If an interrupt or exception is processed after SS has been changed but before ESP has received the corresponding change, the two parts of the stack pointer SS:ESP are inconsistent for the duration of the interrupt handler or exception handler.
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<p>To prevent this situation, the 80386, after both a <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> to SS and a <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> to SS instruction, inhibits NMI, INTR, debug exceptions, and single-step traps at the instruction boundary following the instruction that changes SS. Some exceptions may still occur; namely, page fault and general protection fault. Always use the 80386 <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a> instruction, and the problem will not occur.
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<p>
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<hr>
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<p><b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
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<b>prev:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a><br>
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<b>next:</b> <a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a>
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</body>
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