45 lines
3.5 KiB
HTML
45 lines
3.5 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 9.4</title>
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<b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
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<b>prev:</b> <a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a><br>
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<b>next:</b> <a href="S09_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_05.HTM">9.5 IDT Descriptors</a>
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<p>
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<p>
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<h1>9.4 Interrupt Descriptor Table</h1>
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The interrupt descriptor table (IDT) associates each interrupt or exception identifier with a descriptor for the instructions that service the associated event. Like the GDT and LDTs, the IDT is an array of 8-byte descriptors. Unlike the GDT and LDTs, the first entry of the IDT may contain a descriptor. To form an index into the IDT, the processor multiplies the interrupt or exception identifier by eight. Because there are only 256 identifiers, the IDT need not contain more than 256 descriptors. It can contain fewer than 256 entries; entries are required only for interrupt identifiers that are actually used.
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<p>The IDT may reside anywhere in physical memory. As <a href="#fig9-1">Figure 9-1</a> shows, the processor locates the IDT by means of the IDT register (IDTR). The instructions <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> and <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> operate on the IDTR. Both instructions have one explicit operand: the address in memory of a 6-byte area. <a href="#fig9-2">Figure 9-2</a> shows the format of this area.
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<p><a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> (Load IDT register) loads the IDT register with the linear base address and limit values contained in the memory operand. This instruction can be executed only when the CPL is zero. It is normally used by the initialization logic of an operating system when creating an IDT. An operating system may also use it to change from one IDT to another.
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<p><a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> (Store IDT register) copies the base and limit value stored in IDTR to a memory location. This instruction can be executed at any privilege level. <a name="Table 9-2">
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<pre>
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Table 9-2. Priority Among Simultaneous Interrupts and Exceptions
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Priority Class of Interrupt or Exception
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HIGHEST Faults except debug faults
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Trap instructions INTO, INT n, INT 3
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Debug traps for this instruction
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Debug faults for next instruction
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NMI interrupt
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LOWEST INTR interrupt
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</pre>
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</a><a name="fig9-1"><img align="center" src="FIG9-1.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG9-1.GIF" border="0">
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<p><a name="fig9-2"><img align="center" src="FIG9-2.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG9-2.GIF" border="0">
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<p>
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<hr>
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<p><b>up:</b> <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a><br>
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<b>prev:</b> <a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a><br>
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<b>next:</b> <a href="S09_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_05.HTM">9.5 IDT Descriptors</a>
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</body>
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