630 lines
18 KiB
HTML
630 lines
18 KiB
HTML
<HTML>
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<HEAD>
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<!-- This HTML file has been created by texi2html 1.52
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from ../texi/as.texinfo on 24 April 1999 -->
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<TITLE>Using as - M680x0 Dependent Features</TITLE>
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</HEAD>
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<BODY>
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Go to the <A HREF="as_1.html">first</A>, <A HREF="as_17.html">previous</A>, <A HREF="as_19.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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<P><HR><P>
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<H1><A NAME="SEC214" HREF="as_toc.html#TOC214">M680x0 Dependent Features</A></H1>
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<P>
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<A NAME="IDX666"></A>
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</P>
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<H2><A NAME="SEC215" HREF="as_toc.html#TOC215">M680x0 Options</A></H2>
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<P>
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<A NAME="IDX667"></A>
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<A NAME="IDX668"></A>
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The Motorola 680x0 version of <CODE>as</CODE> has a few machine
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dependent options.
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</P>
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<P>
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<A NAME="IDX669"></A>
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You can use the <SAMP>`-l'</SAMP> option to shorten the size of references to undefined
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symbols. If you do not use the <SAMP>`-l'</SAMP> option, references to undefined
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symbols are wide enough for a full <CODE>long</CODE> (32 bits). (Since
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<CODE>as</CODE> cannot know where these symbols end up, <CODE>as</CODE> can
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only allocate space for the linker to fill in later. Since <CODE>as</CODE>
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does not know how far away these symbols are, it allocates as much space as it
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can.) If you use this option, the references are only one word wide (16 bits).
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This may be useful if you want the object file to be as small as possible, and
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you know that the relevant symbols are always less than 17 bits away.
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</P>
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<P>
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<A NAME="IDX670"></A>
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For some configurations, especially those where the compiler normally
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does not prepend an underscore to the names of user variables, the
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assembler requires a <SAMP>`%'</SAMP> before any use of a register name. This
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is intended to let the assembler distinguish between C variables and
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functions named <SAMP>`a0'</SAMP> through <SAMP>`a7'</SAMP>, and so on. The <SAMP>`%'</SAMP> is
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always accepted, but is not required for certain configurations, notably
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<SAMP>`sun3'</SAMP>. The <SAMP>`--register-prefix-optional'</SAMP> option may be used
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to permit omitting the <SAMP>`%'</SAMP> even for configurations for which it is
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normally required. If this is done, it will generally be impossible to
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refer to C variables and functions with the same names as register
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names.
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</P>
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<P>
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<A NAME="IDX671"></A>
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Normally the character <SAMP>`|'</SAMP> is treated as a comment character, which
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means that it can not be used in expressions. The <SAMP>`--bitwise-or'</SAMP>
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option turns <SAMP>`|'</SAMP> into a normal character. In this mode, you must
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either use C style comments, or start comments with a <SAMP>`#'</SAMP> character
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at the beginning of a line.
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</P>
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<P>
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<A NAME="IDX672"></A>
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<A NAME="IDX673"></A>
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If you use an addressing mode with a base register without specifying
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the size, <CODE>as</CODE> will normally use the full 32 bit value.
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For example, the addressing mode <SAMP>`%a0@(%d0)'</SAMP> is equivalent to
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<SAMP>`%a0@(%d0:l)'</SAMP>. You may use the <SAMP>`--base-size-default-16'</SAMP>
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option to tell <CODE>as</CODE> to default to using the 16 bit value.
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In this case, <SAMP>`%a0@(%d0)'</SAMP> is equivalent to <SAMP>`%a0@(%d0:w)'</SAMP>.
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You may use the <SAMP>`--base-size-default-32'</SAMP> option to restore the
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default behaviour.
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</P>
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<P>
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<A NAME="IDX674"></A>
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<A NAME="IDX675"></A>
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If you use an addressing mode with a displacement, and the value of the
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displacement is not known, <CODE>as</CODE> will normally assume that
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the value is 32 bits. For example, if the symbol <SAMP>`disp'</SAMP> has not
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been defined, <CODE>as</CODE> will assemble the addressing mode
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<SAMP>`%a0@(disp,%d0)'</SAMP> as though <SAMP>`disp'</SAMP> is a 32 bit value. You may
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use the <SAMP>`--disp-size-default-16'</SAMP> option to tell <CODE>as</CODE>
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to instead assume that the displacement is 16 bits. In this case,
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<CODE>as</CODE> will assemble <SAMP>`%a0@(disp,%d0)'</SAMP> as though
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<SAMP>`disp'</SAMP> is a 16 bit value. You may use the
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<SAMP>`--disp-size-default-32'</SAMP> option to restore the default behaviour.
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</P>
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<P>
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<A NAME="IDX676"></A>
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<A NAME="IDX677"></A>
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<A NAME="IDX678"></A>
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<CODE>as</CODE> can assemble code for several different members of the
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Motorola 680x0 family. The default depends upon how <CODE>as</CODE>
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was configured when it was built; normally, the default is to assemble
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code for the 68020 microprocessor. The following options may be used to
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change the default. These options control which instructions and
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addressing modes are permitted. The members of the 680x0 family are
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very similar. For detailed information about the differences, see the
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Motorola manuals.
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</P>
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<DL COMPACT>
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<DT><SAMP>`-m68000'</SAMP>
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<DD>
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<DT><SAMP>`-m68ec000'</SAMP>
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<DD>
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<DT><SAMP>`-m68hc000'</SAMP>
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<DD>
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<DT><SAMP>`-m68hc001'</SAMP>
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<DD>
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<DT><SAMP>`-m68008'</SAMP>
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<DD>
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<DT><SAMP>`-m68302'</SAMP>
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<DD>
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<DT><SAMP>`-m68306'</SAMP>
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<DD>
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<DT><SAMP>`-m68307'</SAMP>
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<DD>
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<DT><SAMP>`-m68322'</SAMP>
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<DD>
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<DT><SAMP>`-m68356'</SAMP>
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<DD>
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Assemble for the 68000. <SAMP>`-m68008'</SAMP>, <SAMP>`-m68302'</SAMP>, and so on are synonyms
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for <SAMP>`-m68000'</SAMP>, since the chips are the same from the point of view
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of the assembler.
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<DT><SAMP>`-m68010'</SAMP>
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<DD>
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Assemble for the 68010.
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<DT><SAMP>`-m68020'</SAMP>
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<DD>
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<DT><SAMP>`-m68ec020'</SAMP>
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<DD>
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Assemble for the 68020. This is normally the default.
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<DT><SAMP>`-m68030'</SAMP>
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<DD>
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<DT><SAMP>`-m68ec030'</SAMP>
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<DD>
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Assemble for the 68030.
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<DT><SAMP>`-m68040'</SAMP>
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<DD>
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<DT><SAMP>`-m68ec040'</SAMP>
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<DD>
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Assemble for the 68040.
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<DT><SAMP>`-m68060'</SAMP>
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<DD>
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<DT><SAMP>`-m68ec060'</SAMP>
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<DD>
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Assemble for the 68060.
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<DT><SAMP>`-mcpu32'</SAMP>
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<DD>
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<DT><SAMP>`-m68330'</SAMP>
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<DD>
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<DT><SAMP>`-m68331'</SAMP>
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<DD>
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<DT><SAMP>`-m68332'</SAMP>
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<DD>
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<DT><SAMP>`-m68333'</SAMP>
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<DD>
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<DT><SAMP>`-m68334'</SAMP>
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<DD>
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<DT><SAMP>`-m68336'</SAMP>
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<DD>
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<DT><SAMP>`-m68340'</SAMP>
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<DD>
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<DT><SAMP>`-m68341'</SAMP>
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<DD>
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<DT><SAMP>`-m68349'</SAMP>
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<DD>
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<DT><SAMP>`-m68360'</SAMP>
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<DD>
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Assemble for the CPU32 family of chips.
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<DT><SAMP>`-m5200'</SAMP>
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<DD>
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Assemble for the ColdFire family of chips.
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<DT><SAMP>`-m68881'</SAMP>
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<DD>
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<DT><SAMP>`-m68882'</SAMP>
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<DD>
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Assemble 68881 floating point instructions. This is the default for the
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68020, 68030, and the CPU32. The 68040 and 68060 always support
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floating point instructions.
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<DT><SAMP>`-mno-68881'</SAMP>
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<DD>
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Do not assemble 68881 floating point instructions. This is the default
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for 68000 and the 68010. The 68040 and 68060 always support floating
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point instructions, even if this option is used.
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<DT><SAMP>`-m68851'</SAMP>
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<DD>
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Assemble 68851 MMU instructions. This is the default for the 68020,
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68030, and 68060. The 68040 accepts a somewhat different set of MMU
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instructions; <SAMP>`-m68851'</SAMP> and <SAMP>`-m68040'</SAMP> should not be used
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together.
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<DT><SAMP>`-mno-68851'</SAMP>
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<DD>
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Do not assemble 68851 MMU instructions. This is the default for the
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68000, 68010, and the CPU32. The 68040 accepts a somewhat different set
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of MMU instructions.
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</DL>
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<H2><A NAME="SEC216" HREF="as_toc.html#TOC216">Syntax</A></H2>
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<P>
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<A NAME="IDX679"></A>
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This syntax for the Motorola 680x0 was developed at MIT.
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</P>
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<P>
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<A NAME="IDX680"></A>
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<A NAME="IDX681"></A>
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<A NAME="IDX682"></A>
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<A NAME="IDX683"></A>
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The 680x0 version of <CODE>as</CODE> uses instructions names and
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syntax compatible with the Sun assembler. Intervening periods are
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ignored; for example, <SAMP>`movl'</SAMP> is equivalent to <SAMP>`mov.l'</SAMP>.
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</P>
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<P>
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In the following table <VAR>apc</VAR> stands for any of the address registers
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(<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP>), the program counter (<SAMP>`%pc'</SAMP>), the
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zero-address relative to the program counter (<SAMP>`%zpc'</SAMP>), a suppressed
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address register (<SAMP>`%za0'</SAMP> through <SAMP>`%za7'</SAMP>), or it may be omitted
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entirely. The use of <VAR>size</VAR> means one of <SAMP>`w'</SAMP> or <SAMP>`l'</SAMP>, and
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it may be omitted, along with the leading colon, unless a scale is also
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specified. The use of <VAR>scale</VAR> means one of <SAMP>`1'</SAMP>, <SAMP>`2'</SAMP>,
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<SAMP>`4'</SAMP>, or <SAMP>`8'</SAMP>, and it may always be omitted along with the
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leading colon.
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</P>
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<P>
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<A NAME="IDX684"></A>
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<A NAME="IDX685"></A>
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The following addressing modes are understood:
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<DL COMPACT>
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<DT><EM>Immediate</EM>
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<DD>
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<SAMP>`#<VAR>number</VAR>'</SAMP>
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<DT><EM>Data Register</EM>
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<DD>
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<SAMP>`%d0'</SAMP> through <SAMP>`%d7'</SAMP>
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<DT><EM>Address Register</EM>
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<DD>
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<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP><BR>
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<SAMP>`%a7'</SAMP> is also known as <SAMP>`%sp'</SAMP>, i.e. the Stack Pointer. <CODE>%a6</CODE>
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is also known as <SAMP>`%fp'</SAMP>, the Frame Pointer.
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<DT><EM>Address Register Indirect</EM>
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<DD>
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<SAMP>`%a0@'</SAMP> through <SAMP>`%a7@'</SAMP>
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<DT><EM>Address Register Postincrement</EM>
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<DD>
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<SAMP>`%a0@+'</SAMP> through <SAMP>`%a7@+'</SAMP>
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<DT><EM>Address Register Predecrement</EM>
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<DD>
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<SAMP>`%a0@-'</SAMP> through <SAMP>`%a7@-'</SAMP>
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<DT><EM>Indirect Plus Offset</EM>
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<DD>
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<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>)'</SAMP>
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<DT><EM>Index</EM>
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<DD>
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<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)'</SAMP>
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The <VAR>number</VAR> may be omitted.
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<DT><EM>Postindex</EM>
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<DD>
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<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>)@(<VAR>onumber</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)'</SAMP>
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The <VAR>onumber</VAR> or the <VAR>register</VAR>, but not both, may be omitted.
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<DT><EM>Preindex</EM>
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<DD>
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<SAMP>`<VAR>apc</VAR>@(<VAR>number</VAR>,<VAR>register</VAR>:<VAR>size</VAR>:<VAR>scale</VAR>)@(<VAR>onumber</VAR>)'</SAMP>
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The <VAR>number</VAR> may be omitted. Omitting the <VAR>register</VAR> produces
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the Postindex addressing mode.
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<DT><EM>Absolute</EM>
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<DD>
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<SAMP>`<VAR>symbol</VAR>'</SAMP>, or <SAMP>`<VAR>digits</VAR>'</SAMP>, optionally followed by
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<SAMP>`:b'</SAMP>, <SAMP>`:w'</SAMP>, or <SAMP>`:l'</SAMP>.
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</DL>
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<H2><A NAME="SEC217" HREF="as_toc.html#TOC217">Motorola Syntax</A></H2>
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<P>
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<A NAME="IDX686"></A>
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<A NAME="IDX687"></A>
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</P>
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<P>
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The standard Motorola syntax for this chip differs from the syntax
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already discussed (see section <A HREF="as_18.html#SEC216">Syntax</A>). <CODE>as</CODE> can
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accept Motorola syntax for operands, even if MIT syntax is used for
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other operands in the same instruction. The two kinds of syntax are
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fully compatible.
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</P>
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<P>
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In the following table <VAR>apc</VAR> stands for any of the address registers
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(<SAMP>`%a0'</SAMP> through <SAMP>`%a7'</SAMP>), the program counter (<SAMP>`%pc'</SAMP>), the
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zero-address relative to the program counter (<SAMP>`%zpc'</SAMP>), or a
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suppressed address register (<SAMP>`%za0'</SAMP> through <SAMP>`%za7'</SAMP>). The use
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of <VAR>size</VAR> means one of <SAMP>`w'</SAMP> or <SAMP>`l'</SAMP>, and it may always be
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omitted along with the leading dot. The use of <VAR>scale</VAR> means one of
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<SAMP>`1'</SAMP>, <SAMP>`2'</SAMP>, <SAMP>`4'</SAMP>, or <SAMP>`8'</SAMP>, and it may always be omitted
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along with the leading asterisk.
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</P>
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<P>
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The following additional addressing modes are understood:
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</P>
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<DL COMPACT>
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<DT><EM>Address Register Indirect</EM>
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<DD>
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<SAMP>`(%a0)'</SAMP> through <SAMP>`(%a7)'</SAMP><BR>
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<SAMP>`%a7'</SAMP> is also known as <SAMP>`%sp'</SAMP>, i.e. the Stack Pointer. <CODE>%a6</CODE>
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is also known as <SAMP>`%fp'</SAMP>, the Frame Pointer.
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<DT><EM>Address Register Postincrement</EM>
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<DD>
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<SAMP>`(%a0)+'</SAMP> through <SAMP>`(%a7)+'</SAMP>
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<DT><EM>Address Register Predecrement</EM>
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<DD>
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<SAMP>`-(%a0)'</SAMP> through <SAMP>`-(%a7)'</SAMP>
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<DT><EM>Indirect Plus Offset</EM>
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<DD>
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<SAMP>`<VAR>number</VAR>(<VAR>%a0</VAR>)'</SAMP> through <SAMP>`<VAR>number</VAR>(<VAR>%a7</VAR>)'</SAMP>,
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or <SAMP>`<VAR>number</VAR>(<VAR>%pc</VAR>)'</SAMP>.
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The <VAR>number</VAR> may also appear within the parentheses, as in
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<SAMP>`(<VAR>number</VAR>,<VAR>%a0</VAR>)'</SAMP>. When used with the <VAR>pc</VAR>, the
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<VAR>number</VAR> may be omitted (with an address register, omitting the
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<VAR>number</VAR> produces Address Register Indirect mode).
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<DT><EM>Index</EM>
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<DD>
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<SAMP>`<VAR>number</VAR>(<VAR>apc</VAR>,<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>)'</SAMP>
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The <VAR>number</VAR> may be omitted, or it may appear within the
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parentheses. The <VAR>apc</VAR> may be omitted. The <VAR>register</VAR> and the
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<VAR>apc</VAR> may appear in either order. If both <VAR>apc</VAR> and
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<VAR>register</VAR> are address registers, and the <VAR>size</VAR> and <VAR>scale</VAR>
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are omitted, then the first register is taken as the base register, and
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the second as the index register.
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<DT><EM>Postindex</EM>
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<DD>
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<SAMP>`([<VAR>number</VAR>,<VAR>apc</VAR>],<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>,<VAR>onumber</VAR>)'</SAMP>
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The <VAR>onumber</VAR>, or the <VAR>register</VAR>, or both, may be omitted.
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Either the <VAR>number</VAR> or the <VAR>apc</VAR> may be omitted, but not both.
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<DT><EM>Preindex</EM>
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<DD>
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<SAMP>`([<VAR>number</VAR>,<VAR>apc</VAR>,<VAR>register</VAR>.<VAR>size</VAR>*<VAR>scale</VAR>],<VAR>onumber</VAR>)'</SAMP>
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The <VAR>number</VAR>, or the <VAR>apc</VAR>, or the <VAR>register</VAR>, or any two of
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them, may be omitted. The <VAR>onumber</VAR> may be omitted. The
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<VAR>register</VAR> and the <VAR>apc</VAR> may appear in either order. If both
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<VAR>apc</VAR> and <VAR>register</VAR> are address registers, and the <VAR>size</VAR>
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and <VAR>scale</VAR> are omitted, then the first register is taken as the
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base register, and the second as the index register.
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</DL>
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<H2><A NAME="SEC218" HREF="as_toc.html#TOC218">Floating Point</A></H2>
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<P>
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<A NAME="IDX688"></A>
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<A NAME="IDX689"></A>
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Packed decimal (P) format floating literals are not supported.
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Feel free to add the code!
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</P>
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<P>
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The floating point formats generated by directives are these.
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</P>
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<DL COMPACT>
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<DT><CODE>.float</CODE>
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<DD>
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<A NAME="IDX690"></A>
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<CODE>Single</CODE> precision floating point constants.
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<A NAME="IDX691"></A>
|
|
<DT><CODE>.double</CODE>
|
|
<DD>
|
|
<CODE>Double</CODE> precision floating point constants.
|
|
|
|
<A NAME="IDX692"></A>
|
|
<A NAME="IDX693"></A>
|
|
<DT><CODE>.extend</CODE>
|
|
<DD>
|
|
<DT><CODE>.ldouble</CODE>
|
|
<DD>
|
|
<CODE>Extended</CODE> precision (<CODE>long double</CODE>) floating point constants.
|
|
</DL>
|
|
|
|
|
|
|
|
<H2><A NAME="SEC219" HREF="as_toc.html#TOC219">680x0 Machine Directives</A></H2>
|
|
|
|
<P>
|
|
<A NAME="IDX694"></A>
|
|
<A NAME="IDX695"></A>
|
|
In order to be compatible with the Sun assembler the 680x0 assembler
|
|
understands the following directives.
|
|
|
|
</P>
|
|
<DL COMPACT>
|
|
|
|
<DT><CODE>.data1</CODE>
|
|
<DD>
|
|
<A NAME="IDX696"></A>
|
|
|
|
This directive is identical to a <CODE>.data 1</CODE> directive.
|
|
|
|
<A NAME="IDX697"></A>
|
|
<DT><CODE>.data2</CODE>
|
|
<DD>
|
|
This directive is identical to a <CODE>.data 2</CODE> directive.
|
|
|
|
<A NAME="IDX698"></A>
|
|
<DT><CODE>.even</CODE>
|
|
<DD>
|
|
This directive is a special case of the <CODE>.align</CODE> directive; it
|
|
aligns the output to an even byte boundary.
|
|
|
|
<A NAME="IDX699"></A>
|
|
<DT><CODE>.skip</CODE>
|
|
<DD>
|
|
This directive is identical to a <CODE>.space</CODE> directive.
|
|
</DL>
|
|
|
|
|
|
|
|
<H2><A NAME="SEC220" HREF="as_toc.html#TOC220">Opcodes</A></H2>
|
|
|
|
<P>
|
|
<A NAME="IDX700"></A>
|
|
<A NAME="IDX701"></A>
|
|
<A NAME="IDX702"></A>
|
|
|
|
</P>
|
|
|
|
|
|
|
|
<H3><A NAME="SEC221" HREF="as_toc.html#TOC221">Branch Improvement</A></H3>
|
|
|
|
<P>
|
|
<A NAME="IDX703"></A>
|
|
<A NAME="IDX704"></A>
|
|
<A NAME="IDX705"></A>
|
|
<A NAME="IDX706"></A>
|
|
Certain pseudo opcodes are permitted for branch instructions.
|
|
They expand to the shortest branch instruction that reach the
|
|
target. Generally these mnemonics are made by substituting <SAMP>`j'</SAMP> for
|
|
<SAMP>`b'</SAMP> at the start of a Motorola mnemonic.
|
|
|
|
</P>
|
|
<P>
|
|
The following table summarizes the pseudo-operations. A <CODE>*</CODE> flags
|
|
cases that are more fully described after the table:
|
|
|
|
</P>
|
|
|
|
<PRE>
|
|
Displacement
|
|
+-------------------------------------------------
|
|
| 68020 68000/10
|
|
Pseudo-Op |BYTE WORD LONG LONG non-PC relative
|
|
+-------------------------------------------------
|
|
jbsr |bsrs bsr bsrl jsr jsr
|
|
jra |bras bra bral jmp jmp
|
|
* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp
|
|
* dbXX |dbXX dbXX dbXX; bra; jmpl
|
|
* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp
|
|
|
|
XX: condition
|
|
NX: negative of condition XX
|
|
|
|
</PRE>
|
|
|
|
<P>
|
|
<CODE>*</CODE>---see full description below
|
|
|
|
</P>
|
|
<DL COMPACT>
|
|
|
|
<DT><CODE>jbsr</CODE>
|
|
<DD>
|
|
<DT><CODE>jra</CODE>
|
|
<DD>
|
|
These are the simplest jump pseudo-operations; they always map to one
|
|
particular machine instruction, depending on the displacement to the
|
|
branch target.
|
|
|
|
<DT><CODE>j<VAR>XX</VAR></CODE>
|
|
<DD>
|
|
Here, <SAMP>`j<VAR>XX</VAR>'</SAMP> stands for an entire family of pseudo-operations,
|
|
where <VAR>XX</VAR> is a conditional branch or condition-code test. The full
|
|
list of pseudo-ops in this family is:
|
|
|
|
<PRE>
|
|
jhi jls jcc jcs jne jeq jvc
|
|
jvs jpl jmi jge jlt jgt jle
|
|
</PRE>
|
|
|
|
For the cases of non-PC relative displacements and long displacements on
|
|
the 68000 or 68010, <CODE>as</CODE> issues a longer code fragment in terms of
|
|
<VAR>NX</VAR>, the opposite condition to <VAR>XX</VAR>. For example, for the
|
|
non-PC relative case:
|
|
|
|
<PRE>
|
|
j<VAR>XX</VAR> foo
|
|
</PRE>
|
|
|
|
gives
|
|
|
|
<PRE>
|
|
b<VAR>NX</VAR>s oof
|
|
jmp foo
|
|
oof:
|
|
</PRE>
|
|
|
|
<DT><CODE>db<VAR>XX</VAR></CODE>
|
|
<DD>
|
|
The full family of pseudo-operations covered here is
|
|
|
|
<PRE>
|
|
dbhi dbls dbcc dbcs dbne dbeq dbvc
|
|
dbvs dbpl dbmi dbge dblt dbgt dble
|
|
dbf dbra dbt
|
|
</PRE>
|
|
|
|
Other than for word and byte displacements, when the source reads
|
|
<SAMP>`db<VAR>XX</VAR> foo'</SAMP>, <CODE>as</CODE> emits
|
|
|
|
<PRE>
|
|
db<VAR>XX</VAR> oo1
|
|
bra oo2
|
|
oo1:jmpl foo
|
|
oo2:
|
|
</PRE>
|
|
|
|
<DT><CODE>fj<VAR>XX</VAR></CODE>
|
|
<DD>
|
|
This family includes
|
|
|
|
<PRE>
|
|
fjne fjeq fjge fjlt fjgt fjle fjf
|
|
fjt fjgl fjgle fjnge fjngl fjngle fjngt
|
|
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
|
|
fjor fjseq fjsf fjsne fjst fjueq fjuge
|
|
fjugt fjule fjult fjun
|
|
</PRE>
|
|
|
|
For branch targets that are not PC relative, <CODE>as</CODE> emits
|
|
|
|
<PRE>
|
|
fb<VAR>NX</VAR> oof
|
|
jmp foo
|
|
oof:
|
|
</PRE>
|
|
|
|
when it encounters <SAMP>`fj<VAR>XX</VAR> foo'</SAMP>.
|
|
|
|
</DL>
|
|
|
|
|
|
|
|
<H3><A NAME="SEC222" HREF="as_toc.html#TOC222">Special Characters</A></H3>
|
|
|
|
<P>
|
|
<A NAME="IDX707"></A>
|
|
<A NAME="IDX708"></A>
|
|
<A NAME="IDX709"></A>
|
|
<A NAME="IDX710"></A>
|
|
<A NAME="IDX711"></A>
|
|
<A NAME="IDX712"></A>
|
|
The immediate character is <SAMP>`#'</SAMP> for Sun compatibility. The
|
|
line-comment character is <SAMP>`|'</SAMP> (unless the <SAMP>`--bitwise-or'</SAMP>
|
|
option is used). If a <SAMP>`#'</SAMP> appears at the beginning of a line, it
|
|
is treated as a comment unless it looks like <SAMP>`# line file'</SAMP>, in
|
|
which case it is treated normally.
|
|
|
|
</P>
|
|
|
|
<P><HR><P>
|
|
Go to the <A HREF="as_1.html">first</A>, <A HREF="as_17.html">previous</A>, <A HREF="as_19.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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