48 lines
3.9 KiB
HTML
48 lines
3.9 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Chapter 09</title>
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</head>
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<body>
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<b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
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<b>prev:</b> <a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a><br>
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<b>next:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a>
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<p>
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<hr>
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<p>
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<h1>Chapter 9 Exceptions and Interrupts</h1>
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<p>Interrupts and exceptions are special kinds of control transfer; they work somewhat like unprogrammed <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a>s. They alter the normal program flow to handle external events or to report errors or exceptional conditions. The difference between interrupts and exceptions is that interrupts are used to handle asynchronous events external to the processor, but exceptions handle conditions detected by the processor itself in the course of executing instructions.
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<p>There are two sources for external interrupts and two sources for exceptions:
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<ol>
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<li>Interrupts
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<ul>
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<li>Maskable interrupts, which are signalled via the INTR pin.
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<li>Nonmaskable interrupts, which are signalled via the NMI (Non-Maskable Interrupt) pin.
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</ul>
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<li>Exceptions
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<ul>
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<li>Processor detected. These are further classified as faults, traps, and aborts.
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<li>Programmed. The instructions <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INTO</a>, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> 3, <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a>, and <a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a> can trigger exceptions. These instructions are often called "software interrupts", but the processor handles them as exceptions.
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</ul>
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</ol>
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This chapter explains the features that the 80386 offers for controlling and responding to interrupts when it is executing in protected mode.
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<p><a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a><br>
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<a href="S09_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_02.HTM">9.2 Enabling and Disabling Interrupts</a><br>
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<a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a><br>
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<a href="S09_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM">9.4 Interrupt Descriptor Table</a><br>
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<a href="S09_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_05.HTM">9.5 IDT Descriptors</a><br>
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<a href="S09_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_06.HTM">9.6 Interrupt Tasks and Interrupt Procedures</a><br>
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<a href="S09_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_07.HTM">9.7 Error Code</a><br>
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<a href="S09_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_08.HTM">9.8 Exception Conditions</a><br>
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<a href="S09_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_09.HTM">9.9 Exception Summary</a><br>
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<a href="S09_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_10.HTM">9.10 Error Code Summary</a>
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<p>
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<hr>
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<p><b>up:</b> <a href="TOC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TOC.HTM">Table of Contents</a><br>
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<b>prev:</b> <a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a><br>
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<b>next:</b> <a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a>
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</body>
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