89 lines
8.6 KiB
HTML
89 lines
8.6 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<html>
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<head>
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<title>80386 Programmer's Reference Manual -- Section 4.1</title>
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</head>
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<body>
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<b>up:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>prev:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>next:</b> <a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a>
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<p>
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<hr>
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<p>
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<h1>4.1 Systems Registers</h1>
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The registers designed for use by systems programmers fall into these classes:
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<ul>
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<li>EFLAGS
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<li>Memory-Management Registers
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<li>Control Registers
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<li>Debug Registers
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<li>Test Registers
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</ul>
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<h2>4.1.1 Systems Flags</h2>
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The systems flags of the EFLAGS register control I/O, maskable interrupts, debugging, task switching, and enabling of virtual 8086 execution in a protected, multitasking environment. These flags are highlighted in <a href="#fig4-1">Figure 4-1</a> .
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<dl>
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<dt>IF (Interrupt-Enable Flag, bit 9)
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<dd>Setting IF allows the CPU to recognize external (maskable) interrupt requests. Clearing IF disables these interrupts. IF has no effect on either exceptions or nonmaskable external interrupts . Refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for more details about interrupts .
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<dt>NT (Nested Task, bit 14)
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<dd>The processor uses the nested task flag to control chaining of interrupted and called tasks. NT influences the operation of the <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instruction . Refer to <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7</a> and <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for more information on nested tasks.
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<dt>RF (Resume Flag, bit 16)
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<dd>The RF flag temporarily disables debug exceptions so that an instruction can be restarted after a debug exception without immediately causing another debug exception . Refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> for details .
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<dt>TF (Trap Flag, bit 8)
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<dd>Setting TF puts the processor into single-step mode for debugging. In this mode, the CPU automatically generates an exception after each instruction, allowing a program to be inspected as it executes each instruction. Single-stepping is just one of several debugging features of the 80386 . Refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> for additional information .
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<dt>VM (Virtual 8086 Mode, bit 17)
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<dd>When set, the VM flag indicates that the task is executing an 8086 program . Refer to <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14</a> for a detailed discussion of how the 80386 executes 8086 tasks in a protected, multitasking environment.
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</dl>
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<a name="fig4-1"><img align="center" src="FIG4-1.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG4-1.GIF" border="0">
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<h2>4.1.2 Memory-Management Registers</h2>
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Four registers of the 80386 locate the data structures that control segmented memory management:
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<dl>
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<dt>GDTR Global Descriptor Table Register
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<dt>LDTR Local Descriptor Table Register
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<dd>These registers point to the segment descriptor tables GDT and LDT. Refer to <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5</a> for an explanation of addressing via descriptor tables.
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<dt>IDTR Interrupt Descriptor Table Register
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<dd>This register points to a table of entry points for interrupt handlers (the IDT ) . Refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for details of the interrupt mechanism .
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<dt>TR Task Register
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<dd>This register points to the information needed by the processor to define the current task . Refer to <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7</a> for a description of the multitasking features of the 80386.
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</dl>
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<h2>4.1.3 Control Registers</h2>
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<a href="#fig4-2">Figure 4-2</a> shows the format of the 80386 control registers CR0, CR2, and CR3. These registers are accessible to systems programmers only via variants of the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instruction, which allow them to be loaded from or stored in general registers; for example:
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<pre>
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MOV EAX, CR0
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MOV CR3, EBX
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</pre>
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CR0 contains system control flags, which control or indicate conditions that apply to the system as a whole, not to an individual task.
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<dl>
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<dt>EM (Emulation, bit 2)
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<dd>EM indicates whether coprocessor functions are to be emulated. Refer to <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a> for details .
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<dt>ET (Extension Type, bit 4)
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<dd>ET indicates the type of coprocessor present in the system (80287 or 80387 ) . Refer to <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a> and <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10</a> for details.
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<dt>MP (Math Present, bit 1)
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<dd>MP controls the function of the <a href="WAIT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/WAIT.HTM">WAIT</a> instruction, which is used to coordinate a coprocessor . Refer to <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a> for details .
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<dt>PE (Protection Enable, bit 0)
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<dd>Setting PE causes the processor to begin executing in protected mode. Resetting PE returns to real-address mode . Refer to <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14</a> and <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10</a> for more information on changing processor modes .
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<dt>PG (Paging, bit 31)
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<dd>PG indicates whether the processor uses page tables to translate linear addresses into physical addresses . Refer to <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5</a> for a description of page translation; refer to <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10</a> for a discussion of how to set PG.
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<dt>TS (Task Switched, bit 3)
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<dd>The processor sets TS with every task switch and tests TS when interpreting coprocessor instructions . Refer to <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a> for details .
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</dl>
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CR2 is used for handling page faults when PG is set. The processor stores in CR2 the linear address that triggers the fault . Refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for a description of page-fault handling.
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<p>CR3 is used when PG is set. CR3 enables the processor to locate the page table directory for the current task . Refer to <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5</a> for a description of page tables and page translation.
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<p><a name="fig4-2"><img align="center" src="FIG4-2.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG4-2.GIF" border="0">
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<p>
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<h2>4.1.4 Debug Register</h2>
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The debug registers bring advanced debugging abilities to the 80386, including data breakpoints and the ability to set instruction breakpoints without modifying code segments . Refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> for a complete description of formats and usage.
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<h2>4.1.5 Test Registers</h2>
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The test registers are not a standard part of the 80386 architecture. They are provided solely to enable confidence testing of the translation lookaside buffer (TLB), the cache used for storing information from page tables . <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a> explains how to use these registers .
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<p>
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<hr>
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<p><b>up:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>prev:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>next:</b> <a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a>
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</body>
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