92 lines
6.6 KiB
HTML
92 lines
6.6 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 4.2</title>
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</head>
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<body>
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<b>up:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>prev:</b> <a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a><br>
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<b>next:</b> <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5 -- Memory Management</a>
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<p>
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<hr>
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<p>
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<h1>4.2 Systems Instructions</h1>
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Systems instructions deal with such functions as:
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<ol>
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<li>Verification of pointer parameters (refer to <a href="C06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C06.HTM">Chapter 6</a>):
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<ul>
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<li><a href="ARPL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ARPL.HTM">ARPL> -- Adjust RPL</a>
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<li><a href="LAR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAR.HTM">LAR -- Load Access Rights</a>
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<li><a href="LSL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LSL.HTM">LSL -- Load Segment Limit</a>
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<li><a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERR -- Verify for Reading</a>
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<li><a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERW -- Verify for Writing</a>
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</ul>
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<p>
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<li>Addressing descriptor tables (refer to <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5</a>):
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<ul>
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<li><a href="LLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LLDT.HTM">LLDT -- Load LDT Register</a>
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<li><a href="SLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SLDT.HTM">SLDT -- Store LDT Register</a>
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<li><a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LGDT -- Load GDT Register</a>
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<li><a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SGDT -- Store GDT Register</a>
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</ul>
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<p>
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<li>Multitasking (refer to <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7</a>):
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<ul>
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<li><a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR -- Load Task Register</a>
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<li><a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR -- Store Task Register</a>
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</ul>
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<p>
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<li>Coprocessing and Multiprocessing (refer to <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a>):
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<ul>
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<li><a href="CLTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLTS.HTM">CLTS -- Clear Task-Switched Flag</a>
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<li>ESC -- Escape instructions
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<li><a href="WAIT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/WAIT.HTM">WAIT -- Wait until Coprocessor not Busy</a>
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<li><a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK -- Assert Bus-Lock Signal</a>
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</ul>
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<p>
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<li>Input and Output (refer to <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8</a>):
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<ul>
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<li><a href="IN.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IN.HTM">IN -- Input</a>
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<li><a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM">OUT -- Output</a>
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<li><a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INS -- Input String</a>
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<li><a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTS -- Output String</a>
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</ul>
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<p>
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<li>Interrupt control (refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a>):
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<ul>
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<li><a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI -- Clear Interrupt-Enable Flag</a>
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<li><a href="STI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STI.HTM">STI -- Set Interrupt-Enable Flag</a>
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<li><a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT -- Load IDT Register</a>
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<li><a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT -- Store IDT Register</a>
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</ul>
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<p>
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<li>Debugging (refer to <a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12</a>):
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<ul>
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV -- Move to and from debug registers</a>
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</ul>
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<p>
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<li>TLB testing (refer to <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10</a>):
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<ul>
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV -- Move to and from test registers</a>
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</ul>
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<p>
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<li>System Control:
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<ul>
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<li><a href="SMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SMSW.HTM">SMSW -- Set MSW</a>
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<li><a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM">LMSW -- Load MSW</a>
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<li><a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM">HLT -- Halt Processor</a>
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV -- Move to and from control registers</a>
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</ul>
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</ol>
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The instructions <a href="SMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SMSW.HTM">SMSW</a> and <a href="LMSW.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LMSW.HTM">LMSW</a> are provided for compatibility with the 80286 processor. 80386 programs access the MSW in CR0 via variants of the <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> instruction. <a href="HLT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/HLT.HTM">HLT</a> stops the processor until receipt of an INTR or RESET signal.
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<p>In addition to the chapters cited above, detailed information about each of these instructions can be found in the instruction reference chapter, <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17</a>
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<p>
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<hr>
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<p><b>up:</b> <a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a><br>
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<b>prev:</b> <a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a><br>
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<b>next:</b> <a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5 -- Memory Management</a>
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</body>
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