37 lines
3.0 KiB
HTML
37 lines
3.0 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 10.2</title>
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</head>
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<body>
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<b>up:</b> <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10 -- Initialization</a><br>
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<b>prev:</b> <a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a><br>
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<b>next:</b> <a href="S10_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_03.HTM">10.3 Switching to Protected Mode</a>
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<p>
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<hr>
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<p>
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<h1>10.2 Software Initialization for Real-Address Mode</h1>
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In real-address mode a few structures must be initialized before a program can take advantage of all the features available in this mode.
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<p>
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<h2>10.2.1 Stack</h2>
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No instructions that use the stack can be used until the stack-segment register (SS) has been loaded. SS must point to an area in RAM.
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<p>
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<h2>10.2.2 Interrupt Table</h2>
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The initial state of the 80386 leaves interrupts disabled; however, the processor will still attempt to access the interrupt table if an exception or nonmaskable interrupt (NMI) occurs. Initialization software should take one of the following actions:
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<ul>
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<li>Change the limit value in the IDTR to zero. This will cause a shutdown if an exception or nonmaskable interrupt occurs. (Refer to the 80386 Hardware Reference Manual to see how shutdown is signalled externally.)
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<li>Put pointers to valid interrupt handlers in all positions of the interrupt table that might be used by exceptions or interrupts.
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<li>Change the IDTR to point to a valid interrupt table.
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</ul>
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<h2>10.2.3 First Instructions</h2>
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After RESET, address lines A{31-20} are automatically asserted for instruction fetches. This fact, together with the initial values of CS:IP, causes instruction execution to begin at physical address FFFFFFF0H. Near (intrasegment) forms of control transfer instructions may be used to pass control to other addresses in the upper 64K bytes of the address space. The first far (intersegment) <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> or <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instruction causes A{31-20} to drop low, and the 80386 continues executing instructions in the lower one megabyte of physical memory. This automatic assertion of address lines A{31-20} allows systems designers to use a ROM at the high end of the address space to initialize the system.
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<p>
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<hr>
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<p><b>up:</b> <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10 -- Initialization</a><br>
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<b>prev:</b> <a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a><br>
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<b>next:</b> <a href="S10_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_03.HTM">10.3 Switching to Protected Mode</a>
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</body>
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