61 lines
5.0 KiB
HTML
61 lines
5.0 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 15.1</title>
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<b>up:</b> <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15 -- Virtual 8086 Mode</a><br>
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<b>prev:</b> <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15 -- Virtual 8086 Mode</a><br>
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<b>next:</b> <a href="S15_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_02.HTM">15.2 Structure of a V86 Task</a>
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<p>
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<hr>
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<p>
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<h1>15.1 Executing 8086 Code</h1>
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The processor executes in V86 mode when the VM (virtual machine) bit in the EFLAGS register is set. The processor tests this flag under two general conditions:
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<ol>
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<li>When loading segment registers to know whether to use 8086-style address formation.
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<li>When decoding instructions to determine which instructions are sensitive to IOPL.
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</ol>
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Except for these two modifications to its normal operations, the 80386 in V86 mode operated much as in protected mode.
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<h2>15.1.1 Registers and Instructions</h2>
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The register set available in V86 mode includes all the registers defined for the 8086 plus the new registers introduced by the 80386: FS, GS, debug registers, control registers, and test registers. New instructions that explicitly operate on the segment registers FS and GS are available, and the new segment-override prefixes can be used to cause instructions to utilize FS and GS for address calculations. Instructions can utilize 32-bit operands through the use of the operand size prefix.
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<p>8086 programs running as V86 tasks are able to take advantage of the new applications-oriented instructions added to the architecture by the introduction of the 80186/80188, 80286 and 80386:
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<ul>
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<li>New instructions introduced by 80186/80188 and 80286.
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<ul>
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<li><a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> immediate data
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<li>Push all and pop all (<a href="PUSHA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHA.HTM">PUSHA</a> and <a href="POPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPA.HTM">POPA</a>)
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<li>Multiply immediate data
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<li>Shift and rotate by immediate count
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<li>String I/O
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<li><a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM">ENTER</a> and <a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM">LEAVE</a>
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<li><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a>
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</ul>
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<li>New instructions introduced by 80386.
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<ul>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a> instructions
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<li>Long-displacement conditional jumps
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<li>Single-bit instructions
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<li>Bit scan
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<li>Double-shift instructions
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<li>Byte set on condition
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<li>Move with sign/zero extension
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<li>Generalized multiply
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</ul>
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</ul>
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<h2>15.1.2 Linear Address Formation</h2>
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In V86 mode, the 80386 processor does not interpret 8086 selectors by referring to descriptors; instead, it forms linear addresses as an 8086 would. It shifts the selector left by four bits to form a 20-bit base address. The effective address is extended with four high-order zeros and added to the base address to create a linear address as <a href="#fig15-1">Figure 15-1</a> illustrates.
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<p>Because of the possibility of a carry, the resulting linear address may contain up to 21 significant bits. An 8086 program may generate linear addresses anywhere in the range 0 to 10FFEFH (one megabyte plus approximately 64 Kbytes) of the task's linear address space.
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<p>V86 tasks generate 32-bit linear addresses. While an 8086 program can only utilize the low-order 21 bits of a linear address, the linear address can be mapped via page tables to any 32-bit physical address.
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<p>Unlike the 8086 and 80286, 32-bit effective addresses can be generated (via the address-size prefix); however, the value of a 32-bit address may not exceed 65,535 without causing an exception. For full compatibility with 80286 real-address mode, pseudo-protection faults (interrupt 12 or 13 with no error code) occur if an address is generated outside the range 0 through 65,535.
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<p><a name="fig15-1"><img align="center" src="FIG15-1.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG15-1.GIF" border="0">
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<p>
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<hr>
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<p><b>up:</b> <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15 -- Virtual 8086 Mode</a><br>
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<b>prev:</b> <a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15 -- Virtual 8086 Mode</a><br>
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<b>next:</b> <a href="S15_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_02.HTM">15.2 Structure of a V86 Task</a>
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</body>
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