256 lines
9.5 KiB
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256 lines
9.5 KiB
HTML
<HTML>
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<!-- This HTML file has been created by texi2html 1.52
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from ../texi/as.texinfo on 24 April 1999 -->
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<TITLE>Using as - Intel 80960 Dependent Features</TITLE>
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</HEAD>
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<BODY>
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Go to the <A HREF="as_1.html">first</A>, <A HREF="as_16.html">previous</A>, <A HREF="as_18.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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<P><HR><P>
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<H1><A NAME="SEC207" HREF="as_toc.html#TOC207">Intel 80960 Dependent Features</A></H1>
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<P>
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<A NAME="IDX638"></A>
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</P>
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<H2><A NAME="SEC208" HREF="as_toc.html#TOC208">i960 Command-line Options</A></H2>
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<P>
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<A NAME="IDX639"></A>
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<A NAME="IDX640"></A>
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<DL COMPACT>
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<DT><CODE>-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC</CODE>
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<DD>
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<A NAME="IDX641"></A>
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<A NAME="IDX642"></A>
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<A NAME="IDX643"></A>
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Select the 80960 architecture. Instructions or features not supported
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by the selected architecture cause fatal errors.
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<SAMP>`-ACA'</SAMP> is equivalent to <SAMP>`-ACA_A'</SAMP>; <SAMP>`-AKC'</SAMP> is equivalent to
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<SAMP>`-AMC'</SAMP>. Synonyms are provided for compatibility with other tools.
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If you do not specify any of these options, <CODE>as</CODE> generates code
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for any instruction or feature that is supported by <EM>some</EM> version of the
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960 (even if this means mixing architectures!). In principle,
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<CODE>as</CODE> attempts to deduce the minimal sufficient processor type if
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none is specified; depending on the object code format, the processor type may
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be recorded in the object file. If it is critical that the <CODE>as</CODE>
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output match a specific architecture, specify that architecture explicitly.
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<A NAME="IDX644"></A>
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<A NAME="IDX645"></A>
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<A NAME="IDX646"></A>
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<DT><CODE>-b</CODE>
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<DD>
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Add code to collect information about conditional branches taken, for
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later optimization using branch prediction bits. (The conditional branch
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instructions have branch prediction bits in the CA, CB, and CC
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architectures.) If <VAR>BR</VAR> represents a conditional branch instruction,
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the following represents the code generated by the assembler when
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<SAMP>`-b'</SAMP> is specified:
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<PRE>
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call <VAR>increment routine</VAR>
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.word 0 # pre-counter
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Label: <VAR>BR</VAR>
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call <VAR>increment routine</VAR>
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.word 0 # post-counter
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</PRE>
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The counter following a branch records the number of times that branch
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was <EM>not</EM> taken; the differenc between the two counters is the
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number of times the branch <EM>was</EM> taken.
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<A NAME="IDX647"></A>
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<A NAME="IDX648"></A>
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A table of every such <CODE>Label</CODE> is also generated, so that the
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external postprocessor <CODE>gbr960</CODE> (supplied by Intel) can locate all
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the counters. This table is always labelled <SAMP>`__BRANCH_TABLE__'</SAMP>;
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this is a local symbol to permit collecting statistics for many separate
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object files. The table is word aligned, and begins with a two-word
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header. The first word, initialized to 0, is used in maintaining linked
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lists of branch tables. The second word is a count of the number of
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entries in the table, which follow immediately: each is a word, pointing
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to one of the labels illustrated above.
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The first word of the header is used to locate multiple branch tables,
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since each object file may contain one. Normally the links are
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maintained with a call to an initialization routine, placed at the
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beginning of each function in the file. The GNU C compiler
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generates these calls automatically when you give it a <SAMP>`-b'</SAMP> option.
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For further details, see the documentation of <SAMP>`gbr960'</SAMP>.
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<A NAME="IDX649"></A>
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<DT><CODE>-no-relax</CODE>
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<DD>
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Normally, Compare-and-Branch instructions with targets that require
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displacements greater than 13 bits (or that have external targets) are
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replaced with the corresponding compare (or <SAMP>`chkbit'</SAMP>) and branch
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instructions. You can use the <SAMP>`-no-relax'</SAMP> option to specify that
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<CODE>as</CODE> should generate errors instead, if the target displacement
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is larger than 13 bits.
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This option does not affect the Compare-and-Jump instructions; the code
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emitted for them is <EM>always</EM> adjusted when necessary (depending on
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displacement size), regardless of whether you use <SAMP>`-no-relax'</SAMP>.
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</DL>
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<H2><A NAME="SEC209" HREF="as_toc.html#TOC209">Floating Point</A></H2>
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<P>
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<A NAME="IDX650"></A>
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<A NAME="IDX651"></A>
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<CODE>as</CODE> generates IEEE floating-point numbers for the directives
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<SAMP>`.float'</SAMP>, <SAMP>`.double'</SAMP>, <SAMP>`.extended'</SAMP>, and <SAMP>`.single'</SAMP>.
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</P>
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<H2><A NAME="SEC210" HREF="as_toc.html#TOC210">i960 Machine Directives</A></H2>
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<P>
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<A NAME="IDX652"></A>
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<A NAME="IDX653"></A>
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</P>
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<DL COMPACT>
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<DT><CODE>.bss <VAR>symbol</VAR>, <VAR>length</VAR>, <VAR>align</VAR></CODE>
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<DD>
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<A NAME="IDX654"></A>
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Reserve <VAR>length</VAR> bytes in the bss section for a local <VAR>symbol</VAR>,
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aligned to the power of two specified by <VAR>align</VAR>. <VAR>length</VAR> and
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<VAR>align</VAR> must be positive absolute expressions. This directive
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differs from <SAMP>`.lcomm'</SAMP> only in that it permits you to specify
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an alignment. See section <A HREF="as_7.html#SEC101"><CODE>.lcomm <VAR>symbol</CODE> , <VAR>length</VAR></VAR></A>.
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</DL>
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<DL COMPACT>
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<DT><CODE>.extended <VAR>flonums</VAR></CODE>
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<DD>
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<A NAME="IDX655"></A>
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<CODE>.extended</CODE> expects zero or more flonums, separated by commas; for
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each flonum, <SAMP>`.extended'</SAMP> emits an IEEE extended-format (80-bit)
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floating-point number.
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<A NAME="IDX656"></A>
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<DT><CODE>.leafproc <VAR>call-lab</VAR>, <VAR>bal-lab</VAR></CODE>
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<DD>
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You can use the <SAMP>`.leafproc'</SAMP> directive in conjunction with the
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optimized <CODE>callj</CODE> instruction to enable faster calls of leaf
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procedures. If a procedure is known to call no other procedures, you
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may define an entry point that skips procedure prolog code (and that does
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not depend on system-supplied saved context), and declare it as the
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<VAR>bal-lab</VAR> using <SAMP>`.leafproc'</SAMP>. If the procedure also has an
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entry point that goes through the normal prolog, you can specify that
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entry point as <VAR>call-lab</VAR>.
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A <SAMP>`.leafproc'</SAMP> declaration is meant for use in conjunction with the
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optimized call instruction <SAMP>`callj'</SAMP>; the directive records the data
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needed later to choose between converting the <SAMP>`callj'</SAMP> into a
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<CODE>bal</CODE> or a <CODE>call</CODE>.
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<VAR>call-lab</VAR> is optional; if only one argument is present, or if the
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two arguments are identical, the single argument is assumed to be the
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<CODE>bal</CODE> entry point.
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<A NAME="IDX657"></A>
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<DT><CODE>.sysproc <VAR>name</VAR>, <VAR>index</VAR></CODE>
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<DD>
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The <SAMP>`.sysproc'</SAMP> directive defines a name for a system procedure.
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After you define it using <SAMP>`.sysproc'</SAMP>, you can use <VAR>name</VAR> to
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refer to the system procedure identified by <VAR>index</VAR> when calling
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procedures with the optimized call instruction <SAMP>`callj'</SAMP>.
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Both arguments are required; <VAR>index</VAR> must be between 0 and 31
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(inclusive).
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</DL>
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<H2><A NAME="SEC211" HREF="as_toc.html#TOC211">i960 Opcodes</A></H2>
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<P>
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<A NAME="IDX658"></A>
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<A NAME="IDX659"></A>
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All Intel 960 machine instructions are supported;
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see section <A HREF="as_17.html#SEC208">i960 Command-line Options</A> for a discussion of
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selecting the instruction subset for a particular 960
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architecture.
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</P>
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<P>
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Some opcodes are processed beyond simply emitting a single corresponding
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instruction: <SAMP>`callj'</SAMP>, and Compare-and-Branch or Compare-and-Jump
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instructions with target displacements larger than 13 bits.
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</P>
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<H3><A NAME="SEC212" HREF="as_toc.html#TOC212"><CODE>callj</CODE></A></H3>
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<P>
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<A NAME="IDX660"></A>
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<A NAME="IDX661"></A>
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You can write <CODE>callj</CODE> to have the assembler or the linker determine
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the most appropriate form of subroutine call: <SAMP>`call'</SAMP>,
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<SAMP>`bal'</SAMP>, or <SAMP>`calls'</SAMP>. If the assembly source contains
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enough information--a <SAMP>`.leafproc'</SAMP> or <SAMP>`.sysproc'</SAMP> directive
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defining the operand--then <CODE>as</CODE> translates the
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<CODE>callj</CODE>; if not, it simply emits the <CODE>callj</CODE>, leaving it
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for the linker to resolve.
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</P>
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<H3><A NAME="SEC213" HREF="as_toc.html#TOC213">Compare-and-Branch</A></H3>
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<P>
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<A NAME="IDX662"></A>
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<A NAME="IDX663"></A>
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The 960 architectures provide combined Compare-and-Branch instructions
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that permit you to store the branch target in the lower 13 bits of the
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instruction word itself. However, if you specify a branch target far
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enough away that its address won't fit in 13 bits, the assembler can
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either issue an error, or convert your Compare-and-Branch instruction
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into separate instructions to do the compare and the branch.
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</P>
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<P>
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<A NAME="IDX664"></A>
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<A NAME="IDX665"></A>
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Whether <CODE>as</CODE> gives an error or expands the instruction depends
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on two choices you can make: whether you use the <SAMP>`-no-relax'</SAMP> option,
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and whether you use a "Compare and Branch" instruction or a "Compare
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and Jump" instruction. The "Jump" instructions are <EM>always</EM>
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expanded if necessary; the "Branch" instructions are expanded when
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necessary <EM>unless</EM> you specify <CODE>-no-relax</CODE>---in which case
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<CODE>as</CODE> gives an error instead.
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</P>
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<P>
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These are the Compare-and-Branch instructions, their "Jump" variants,
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and the instruction pairs they may expand into:
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</P>
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<P><HR><P>
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Go to the <A HREF="as_1.html">first</A>, <A HREF="as_16.html">previous</A>, <A HREF="as_18.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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</BODY>
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</HTML>
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