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84 lines
9.3 KiB
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<title>80386 Programmer's Reference Manual -- Section 3.10</title>
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<body>
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<b>up:</b> <a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">Chapter 3 -- Applications Instruction Set</a><br>
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<b>prev:</b> <a href="S03_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_09.HTM">3.9 Coprocessor Interface Instructions</a><br>
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<b>next:</b> <a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a>
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<p>
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<hr>
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<p>
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<h1>3.10 Segment Register Instructions</h1>
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This category actually includes several distinct types of instructions. These various types are grouped together here because, if systems designers choose an unsegmented model of memory organization, none of these instructions is used by applications programmers. The instructions that deal with segment registers are:
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<ol>
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<li>Segment-register transfer instructions.
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<ul>
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<li><a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> SegReg, ...
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<li><a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> ..., SegReg
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<li><a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> SegReg
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<li><a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> SegReg
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</ul>
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<li>Control transfers to another executable segment.
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<ul>
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<li><a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> far direct and indirect
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<li><a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> far
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<li><a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> far
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</ul>
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<li>Data pointer instructions.
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<ul>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LES</a>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a>
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a>
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</ul>
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</ol>
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Note that the following interrupt-related instructions are different; all are capable of transferring control to another segment, but the use of segmentation is not apparent to the applications programmer.
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<p>
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<ul>
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<li><a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT n</a>
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<li><a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INTO</a>
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<li><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a>
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<li><a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a>
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</ul>
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<h2>3.10.1 Segment-Register Transfer Instructions</h2>
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The <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a>, <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a>, and <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> instructions also serve to load and store segment registers. These variants operate similarly to their general-register counterparts except that one operand can be a segment register. <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> cannot move segment register to a segment register. Neither <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> nor <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> can place a value in the code-segment register CS; only the far control-transfer instructions can change CS.
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<h2>3.10.2 Far Control Transfer Instructions</h2>
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The far control-transfer instructions transfer control to a location in another segment by changing the content of the CS register.
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<p>Direct far <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>. Direct <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instructions that specify a target location outside the current code segment contain a far pointer. This pointer consists of a selector for the new code segment and an offset within the new segment.
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<p>Indirect far <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>. Indirect <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instructions that specify a target location outside the current code segment use a 48-bit variable to specify the far pointer.
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<p>Far <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a>. An intersegment <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> places both the value of EIP and CS on the stack.
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<p>Far <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a>. An intersegment <a href="RET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/RET.HTM">RET</a> restores the values of both CS and EIP which were saved on the stack by the previous intersegment <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instruction.
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<h2>3.10.3 Data Pointer Instructions</h2>
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The data pointer instructions load a pointer (consisting of a segment selector and an offset) to a segment register and a general register.
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<p><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> (Load Pointer Using DS) transfers a pointer variable from the source operand to DS and the destination register. The source operand must be a memory operand, and the destination operand must be a general register. DS receives the segment-selector of the pointer. The destination register receives the offset part of the pointer, which points to a specific location within the segment. Example:
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<pre>
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<a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> ESI, STRING_X
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</pre>
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Loads DS with the selector identifying the segment pointed to by a STRING_X, and loads the offset of STRING_X into ESI. Specifying ESI as the destination operand is a convenient way to prepare for a string operation on a source string that is not in the current data segment.
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<p><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LES</a> (Load Pointer Using ES) operates identically to <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> except that ES receives the segment selector rather than DS. Example:
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<pre>
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<a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LES</a> EDI, DESTINATION_X
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</pre>
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Loads ES with the selector identifying the segment pointed to by DESTINATION_X, and loads the offset of DESTINATION_X into EDI. This instruction provides a convenient way to select a destination for a string operation if the desired location is not in the current extra segment.
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<p><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a> (Load Pointer Using FS) operates identically to <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> except that FS receives the segment selector rather than DS.
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<p><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a> (Load Pointer Using GS) operates identically to <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> except that GS receives the segment selector rather than DS.
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<p><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a> (Load Pointer Using SS) operates identically to <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LDS</a> except that SS receives the segment selector rather than DS. This instruction is especially important, because it allows the two registers that identify the stack (SS:ESP) to be changed in one uninterruptible operation. Unlike the other instructions which load SS, interrupts are not inhibited at the end of the <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a> instruction. The other instructions (e.g., <a href="POP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POP.HTM">POP</a> SS) inhibit interrupts to permit the following instruction to load ESP, thereby forming an indivisible load of SS:ESP. Since both SS and ESP can be loaded by <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a>, there is no need to inhibit interrupts.
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<p>
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<hr>
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<p><b>up:</b> <a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">Chapter 3 -- Applications Instruction Set</a><br>
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<b>prev:</b> <a href="S03_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_09.HTM">3.9 Coprocessor Interface Instructions</a><br>
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<b>next:</b> <a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a>
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</body>
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