29 lines
3.4 KiB
HTML
29 lines
3.4 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
|
|
<html>
|
|
|
|
<head>
|
|
<title>80386 Programmer's Reference Manual -- Section 7.3</title>
|
|
</head>
|
|
|
|
<body>
|
|
<b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
|
|
<b>prev:</b> <a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a><br>
|
|
<b>next:</b> <a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a>
|
|
<p>
|
|
<hr>
|
|
<p>
|
|
<h1>7.3 Task Register</h1>
|
|
The task register (TR) identifies the currently executing task by pointing to the TSS. <a href="#fig7-3">Figure 7-3</a> shows the path by which the processor accesses the current TSS.
|
|
<p>The task register has both a "visible" portion (i.e., can be read and changed by instructions) and an "invisible" portion (maintained by the processor to correspond to the visible portion; cannot be read by any instruction). The selector in the visible portion selects a TSS descriptor in the GDT. The processor uses the invisible portion to cache the base and limit values from the TSS descriptor. Holding the base and limit in a register makes execution of the task more efficient, because the processor does not need to repeatedly fetch these values from memory when it references the TSS of the current task.
|
|
<p>The instructions <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> and <a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR</a> are used to modify and read the visible portion of the task register. Both instructions take one operand, a 16-bit selector located in memory or in a general register.
|
|
<p><a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> (Load task register) loads the visible portion of the task register with the selector operand, which must select a TSS descriptor in the GDT. <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> also loads the invisible portion with information from the TSS descriptor selected by the operand. <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> is a privileged instruction; it may be executed only when CPL is zero. <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a> is generally used during system initialization to give an initial value to the task register; thereafter, the contents of TR are changed by task switch operations.
|
|
<p><a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR</a> (Store task register) stores the visible portion of the task register in a general register or memory word. <a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR</a> is not privileged.
|
|
<p><a name="fig7-3"><img align="center" src="FIG7-3.GIF" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/FIG7-3.GIF" border="0">
|
|
<p>
|
|
<hr>
|
|
<p><b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
|
|
<b>prev:</b> <a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a><br>
|
|
<b>next:</b> <a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a>
|
|
</body>
|
|
|