96 lines
9.1 KiB
HTML
96 lines
9.1 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 7.5</title>
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</head>
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<body>
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<b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>prev:</b> <a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a><br>
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<b>next:</b> <a href="S07_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_06.HTM">7.6 Task Linking</a>
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<p>
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<hr>
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<p>
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<h1>7.5 Task Switching</h1>
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The 80386 switches execution to another task in any of four cases:
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<ol>
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<li>The current task executes a <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> or <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> that refers to a TSS descriptor.
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<li>The current task executes a <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> or <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> that refers to a task gate.
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<li>An interrupt or exception vectors to a task gate in the IDT.
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<li>The current task executes an <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> when the NT flag is set.
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</ol>
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<a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>, <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a>, <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a>, interrupts, and exceptions are all ordinary mechanisms of the 80386 that can be used in circumstances that do not require a task switch. Either the type of descriptor referenced or the NT (nested task) bit in the flag word distinguishes between the standard mechanism and the variant that causes a task switch.
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<p>To cause a task switch, a <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> or <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instruction can refer either to a TSS descriptor or to a task gate. The effect is the same in either case: the 80386 switches to the indicated task.
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<p>An exception or interrupt causes a task switch when it vectors to a task gate in the IDT. If it vectors to an interrupt or trap gate in the IDT, a task switch does not occur . Refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for more information on the interrupt mechanism.
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<p>Whether invoked as a task or as a procedure of the interrupted task, an interrupt handler always returns control to the interrupted procedure in the interrupted task. If the NT flag is set, however, the handler is an interrupt task, and the <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> switches back to the interrupted task.
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<p>A task switching operation involves these steps:
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<ol>
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<li>Checking that the current task is allowed to switch to the designated task. Data-access privilege rules apply in the case of <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> or <a href="CALL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CALL.HTM">CALL</a> instructions. The DPL of the TSS descriptor or task gate must be numerically greater (e.g., lower privilege level) than or equal to the maximum of CPL and the RPL of the gate selector. Exceptions, interrupts, and <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> are permitted to switch tasks regardless of the DPL of the target task gate or TSS descriptor.
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<li>Checking that the TSS descriptor of the new task is marked present and has a valid limit. Any errors up to this point occur in the context of the outgoing task. Errors are restartable and can be handled in a way that is transparent to applications procedures.
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<li>Saving the state of the current task. The processor finds the base address of the current TSS cached in the task register. It copies the registers into the current TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI, ES, CS, SS, DS, FS, GS, and the flag register). The EIP field of the TSS points to the instruction after the one that caused the task switch.
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<li>Loading the task register with the selector of the incoming task's TSS descriptor, marking the incoming task's TSS descriptor as busy, and setting the TS (task switched) bit of the MSW. The selector is either the operand of a control transfer instruction or is taken from a task gate.
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<li>Loading the incoming task's state from its TSS and resuming execution. The registers loaded are the LDT register; the flag register; the general registers EIP, EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; the segment registers ES, CS, SS, DS, FS, and GS; and PDBR. Any errors detected in this step occur in the context of the incoming task. To an exception handler, it appears that the first instruction of the new task has not yet executed.
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</ol>
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Note that the state of the outgoing task is always saved when a task switch occurs. If execution of that task is resumed, it starts after the instruction that caused the task switch. The registers are restored to the values they held when the task stopped executing.
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<p>Every task switch sets the TS (task switched) bit in the MSW (machine status word). The TS flag is useful to systems software when a coprocessor (such as a numerics coprocessor) is present. The TS bit signals that the context of the coprocessor may not correspond to the current 80386 task. <a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11</a> discusses the TS bit and coprocessors in more detail .
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<p>Exception handlers that field task-switch exceptions in the incoming task (exceptions due to tests 4 thru 16 of Table 7-1) should be cautious about taking any action that might load the selector that caused the exception. Such an action will probably cause another exception, unless the exception handler first examines the selector and fixes any potential problem.
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<p>The privilege level at which execution resumes in the incoming task is neither restricted nor affected by the privilege level at which the outgoing task was executing. Because the tasks are isolated by their separate address spaces and TSSs and because privilege rules can be used to prevent improper access to a TSS, no privilege rules are needed to constrain the relation between the CPLs of the tasks. The new task begins executing at the privilege level indicated by the RPL of the CS selector value that is loaded from the TSS.
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<pre>
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Table 7-1. Checks Made during a Task Switch
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NP = Segment-not-present exception
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GP = General protection fault
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TS = Invalid TSS
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SF = Stack fault
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Validity tests of a selector check that the selector is in the proper
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table (e.g., the LDT selector refers to the GDT), lies within the bounds of
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the table, and refers to the proper type of descriptor (e.g., the LDT
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selector refers to an LDT descriptor).
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Test Test Description Exception Error Code Selects
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1 Incoming TSS descriptor is
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present NP Incoming TSS
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2 Incoming TSS descriptor is
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marked not-busy GP Incoming TSS
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marked not-busy
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3 Limit of incoming TSS is
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greater than or equal to 103 TS Incoming TSS
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-- All register and selector values are loaded --
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4 LDT selector of incoming
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task is valid TS Incoming TSS
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5 LDT of incoming task is
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present TS Incoming TSS
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6 CS selector is valid TS Code segment
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7 Code segment is present NP Code segment
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8 Code segment DPL matches
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CS RPL TS Code segment
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9 Stack segment is valid GP Stack segment
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10 Stack segment is present SF Stack segment
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11 Stack segment DPL = CPL SF Stack segment
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12 Stack-selector RPL = CPL GP Stack segment
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13 DS, ES, FS, GS selectors are
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valid GP Segment
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14 DS, ES, FS, GS segments
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are readable GP Segment
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15 DS, ES, FS, GS segments
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are present NP Segment
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16 DS, ES, FS, GS segment DPL
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>= CPL (unless these are
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conforming segments) GP Segment
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</pre>
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<p>
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<hr>
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<p><b>up:</b> <a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a><br>
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<b>prev:</b> <a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a><br>
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<b>next:</b> <a href="S07_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_06.HTM">7.6 Task Linking</a>
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</body>
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