48 lines
4.8 KiB
HTML
48 lines
4.8 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 8.1</title>
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</head>
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<body>
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<b>up:</b> <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8 -- Input/Output</a><br>
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<b>prev:</b> <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8 -- Input/Output</a><br>
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<b>next:</b> <a href="S08_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_02.HTM">8.2 I/O Instructions</a>
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<p>
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<hr>
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<p>
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<h1>8.1 I/O Addressing</h1>
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The 80386 allows input/output to be performed in either of two ways:
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<ul>
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<li>By means of a separate I/O address space (using specific I/O instructions)
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<li>By means of memory-mapped I/O (using general-purpose operand manipulation instructions).
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</ul>
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<h2>8.1.1 I/O Address Space</h2>
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The 80386 provides a separate I/O address space, distinct from physical memory, that can be used to address the input/output ports that are used for external 16 devices. The I/O address space consists of 2^(16) (64K) individually addressable 8-bit ports; any two consecutive 8-bit ports can be treated as a 16-bit port; and four consecutive 8-bit ports can be treated as a 32-bit port. Thus, the I/O address space can accommodate up to 64K 8-bit ports, up to 32K 16-bit ports, or up to 16K 32-bit ports.
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<p>The program can specify the address of the port in two ways. Using an immediate byte constant, the program can specify:
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<ul>
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<li>256 8-bit ports numbered 0 through 255.
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<li>128 16-bit ports numbered 0, 2, 4, . . . , 252, 254.
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<li>64 32-bit ports numbered 0, 4, 8, . . . , 248, 252.
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</ul>
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Using a value in DX, the program can specify:
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<ul>
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<li>8-bit ports numbered 0 through 65535
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<li>16-bit ports numbered 0, 2, 4, . . . , 65532, 65534
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<li>32-bit ports numbered 0, 4, 8, . . . , 65528, 65532
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</ul>
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The 80386 can transfer 32, 16, or 8 bits at a time to a device located in the I/O space. Like doublewords in memory, 32-bit ports should be aligned at addresses evenly divisible by four so that the 32 bits can be transferred in a single bus access. Like words in memory, 16-bit ports should be aligned at even-numbered addresses so that the 16 bits can be transferred in a single bus access. An 8-bit port may be located at either an even or odd address.
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<p>The instructions <a href="IN.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IN.HTM">IN</a> and <a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM">OUT</a> move data between a register and a port in the I/O address space. The instructions <a href="INS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INS.HTM">INS</a> and <a href="OUTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUTS.HTM">OUTS</a> move strings of data between the memory address space and ports in the I/O address space.
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<h2>8.1.2 Memory-Mapped I/O</h2>
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I/O devices also may be placed in the 80386 memory address space. As long as the devices respond like memory components, they are indistinguishable to the processor.
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<p>Memory-mapped I/O provides additional programming flexibility. Any instruction that references memory may be used to access an I/O port located in the memory space. For example, the <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> instruction can transfer data between any register and a port; and the <a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND</a>, <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a>, and <a href="TEST.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/TEST.HTM">TEST</a> instructions may be used to manipulate bits in the internal registers of a device (see <a href="S08_02.HTM#fig8-1" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_02.HTM#fig8-1">Figure 8-1</a> ). Memory-mapped I/O performed via the full instruction set maintains the full complement of addressing modes for selecting the desired I/O device (e.g., direct address, indirect address, base register, index register, scaling).
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<p>Memory-mapped I/O, like any other memory reference, is subject to access protection and control when executing in protected mode. Refer to <a href="C06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C06.HTM">Chapter 6</a> for a discussion of memory protection.
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<p>
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<hr>
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<p><b>up:</b> <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8 -- Input/Output</a><br>
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<b>prev:</b> <a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8 -- Input/Output</a><br>
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<b>next:</b> <a href="S08_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_02.HTM">8.2 I/O Instructions</a>
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</body>
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