25 lines
2.0 KiB
HTML
25 lines
2.0 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 10.3</title>
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<b>up:</b> <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10 -- Initialization</a><br>
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<b>prev:</b> <a href="S10_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_02.HTM">10.2 Software Initialization for Real-Address Mode</a><br>
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<b>next:</b> <a href="S10_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_04.HTM">10.4 Software Initialization for Protected Mode</a>
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<hr>
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<p>
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<h1>10.3 Switching to Protected Mode</h1>
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Setting the PE bit of the MSW in CR0 causes the 80386 to begin executing in protected mode. The current privilege level (CPL) starts at zero. The segment registers continue to point to the same linear addresses as in real address mode (in real address mode, linear addresses are the same physical addresses).
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<p>Immediately after setting the PE flag, the initialization code must flush the processor's instruction prefetch queue by executing a <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> instruction. The 80386 fetches and decodes instructions and addresses before they are used; however, after a change into protected mode, the prefetched instruction information (which pertains to real-address mode) is no longer valid. A <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a> forces the processor to discard the invalid information.
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<p>
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<hr>
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<p><b>up:</b> <a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10 -- Initialization</a><br>
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<b>prev:</b> <a href="S10_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_02.HTM">10.2 Software Initialization for Real-Address Mode</a><br>
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<b>next:</b> <a href="S10_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_04.HTM">10.4 Software Initialization for Protected Mode</a>
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</body>
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