51 lines
4.4 KiB
HTML
51 lines
4.4 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 14.2</title>
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<b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a><br>
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<b>next:</b> <a href="S14_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_03.HTM">14.3 Interrupt and Exception Handling</a>
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<h1>14.2 Registers and Instructions</h1>
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The register set available in real-address mode includes all the registers defined for the 8086 plus the new registers introduced by the 80386: FS, GS, debug registers, control registers, and test registers. New instructions that explicitly operate on the segment registers FS and GS are available, and the new segment-override prefixes can be used to cause instructions to utilize FS and GS for address calculations. Instructions can utilize 32-bit operands through the use of the operand size prefix.
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<p>The instruction codes that cause undefined opcode traps (interrupt 6) include instructions of the protected mode that manipulate or interrogate 80386 selectors and descriptors; namely, <a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERR</a>, <a href="VERR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/VERR.HTM">VERW</a>, <a href="LAR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LAR.HTM">LAR</a>, <a href="LSL.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LSL.HTM">LSL</a>, <a href="LTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LTR.HTM">LTR</a>, <a href="STR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/STR.HTM">STR</a>, <a href="LLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LLDT.HTM">LLDT</a>, and <a href="SLDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SLDT.HTM">SLDT</a>. Programs executing in real-address mode are able to take advantage of the new applications-oriented instructions added to the architecture by the introduction of the 80186/80188, 80286 and 80386:
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<ul>
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<li>New instructions introduced by 80186/80188 and 80286.
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<ul>
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<li><a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> immediate data
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<li>Push all and pop all (<a href="PUSHA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHA.HTM">PUSHA</a> and <a href="POPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/POPA.HTM">POPA</a>)
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<li>Multiply immediate data
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<li>Shift and rotate by immediate count
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<li>String I/O
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<li><a href="ENTER.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ENTER.HTM">ENTER</a> and <a href="LEAVE.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LEAVE.HTM">LEAVE</a>
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<li><a href="BOUND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BOUND.HTM">BOUND</a>
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</ul>
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<li>New instructions introduced by 80386.
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<li><a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LSS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LFS</a>, <a href="LGS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGS.HTM">LGS</a> instructions
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<li>Long-displacement conditional jumps
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<li>Single-bit instructions
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<li>Bit scan
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<li>Double-shift instructions
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<li>Byte set on condition
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<li>Move with sign/zero extension
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<li>Generalized multiply
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> to and from control registers
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> to and from test registers
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<li><a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> to and from debug registers
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</ul>
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</ul>
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<p>
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<hr>
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<p><b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a><br>
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<b>next:</b> <a href="S14_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_03.HTM">14.3 Interrupt and Exception Handling</a>
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</body>
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