25 lines
3.0 KiB
HTML
25 lines
3.0 KiB
HTML
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<title>80386 Programmer's Reference Manual -- Section 14.3</title>
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<b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_02.HTM">14.2 Registers and Instructions</a><br>
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<b>next:</b> <a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a>
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<h1>14.3 Interrupt and Exception Handling</h1>
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Interrupts and exceptions in 80386 real-address mode work as much as they do on an 8086. Interrupts and exceptions vector to interrupt procedures via an interrupt table. The processor multiplies the interrupt or exception identifier by four to obtain an index into the interrupt table. The entries of the interrupt table are far pointers to the entry points of interrupt or exception handler procedures. When an interrupt occurs, the processor pushes the current values of CS:IP onto the stack, disables interrupts, clears TF (the single-step flag), then transfers control to the location specified in the interrupt table. An <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instruction at the end of the handler procedure reverses these steps before returning control to the interrupted procedure.
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<p>The primary difference in the interrupt handling of the 80386 compared to the 8086 is that the location and size of the interrupt table depend on the contents of the IDTR (IDT register). Ordinarily, this fact is not apparent to programmers, because, after RESET, the IDTR contains a base address of 0 and a limit of 3FFH, which is compatible with the 8086. However, the <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> instruction can be used in real-address mode to change the base and limit values in the IDTR . Refer to <a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9</a> for details on the IDTR , and the <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> and <a href="SGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SGDT.HTM">SIDT</a> instructions. If an interrupt occurs and the corresponding entry of the interrupt table is beyond the limit stored in the IDTR, the processor raises exception 8.
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<p>
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<hr>
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<p><b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_02.HTM">14.2 Registers and Instructions</a><br>
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<b>next:</b> <a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a>
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</body>
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