48 lines
2.9 KiB
HTML
48 lines
2.9 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<title>80386 Programmer's Reference Manual -- Section 14.5</title>
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</head>
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<body>
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<b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a><br>
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<b>next:</b> <a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a>
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<p>
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<hr>
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<p>
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<h1>14.5 Switching Back to Real-Address Mode</h1>
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The processor reenters real-address mode if software clears the PE bit in CR0 with a <a href="MOVRS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOVRS.HTM">MOV</a> to CR0 instruction. A procedure that attempts to do this, however, should proceed as follows:
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<ol>
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<li>If paging is enabled, perform the following sequence:
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<ul>
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<li>Transfer control to linear addresses that have an identity mapping; i.e., linear addresses equal physical addresses.
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<li>Clear the PG bit in CR0.
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<li>Move zeros to CR3 to clear out the paging cache.
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</ul>
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<li>Transfer control to a segment that has a limit of 64K (FFFFH). This loads the CS register with the limit it needs to have in real mode.
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<li>Load segment registers SS, DS, ES, FS, and GS with a selector that points to a descriptor containing the following values, which are appropriate to real mode:
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<ul>
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<li>Limit = 64K (FFFFH)
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<li>Byte granular (G = 0)
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<li>Expand up (E = 0)
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<li>Writable (W = 1)
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<li>Present (P = 1)
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<li>Base = any value
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</ul>
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<li>Disable interrupts. A <a href="CLI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/CLI.HTM">CLI</a> instruction disables INTR interrupts. NMIs can be disabled with external circuitry.
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<li>Clear the PE bit.
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<li>Jump to the real mode code to be executed using a far <a href="JMP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/JMP.HTM">JMP</a>. This action flushes the instruction queue and puts appropriate values in the access rights of the CS register.
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<li>Use the <a href="LGDT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LGDT.HTM">LIDT</a> instruction to load the base and limit of the real-mode interrupt vector table.
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<li>Enable interrupts.
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<li>Load the segment registers as needed by the real-mode code.
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</ol>
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<p>
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<hr>
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<p><b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a><br>
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<b>next:</b> <a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a>
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</body>
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