165 lines
13 KiB
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165 lines
13 KiB
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<title>80386 Programmer's Reference Manual -- Section 14.7</title>
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</head>
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<body>
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<b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a><br>
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<b>next:</b> <a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a>
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<p>
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<hr>
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<p>
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<h1>14.7 Differences From 8086</h1>
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In general, the 80386 in real-address mode will correctly execute ROM-based software designed for the 8086, 8088, 80186, and 80188. Following is a list of the minor differences between 8086 execution on the 80386 and on an 8086.
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<ol>
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<li>Instruction clock counts.
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<p>The 80386 takes fewer clocks for most instructions than the 8086/8088. The areas most likely to be affected are:
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<ul>
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<p>
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<li>Delays required by I/O devices between I/O operations.
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<p>
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<li>Assumed delays with 8086/8088 operating in parallel with an 8087.
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</ul>
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<p>
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<li>Divide Exceptions Point to the <a href="DIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DIV.HTM">DIV</a> instruction.
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<p>Divide exceptions on the 80386 always leave the saved CS:IP value pointing to the instruction that failed. On the 8086/8088, the CS:IP value points to the next instruction.
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<p>
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<li>Undefined 8086/8088 opcodes.
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<p>Opcodes that were not defined for the 8086/8088 will cause exception 6 or will execute one of the new instructions defined for the 80386.
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<p>
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<li>Value written by <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> SP.
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<p>The 80386 pushes a different value on the stack for <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> SP than the 8086/8088. The 80386 pushes the value of SP before SP is incremented as part of the push operation; the 8086/8088 pushes the value of SP after it is incremented. If the value pushed is important, replace <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> SP instructions with the following three instructions:
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<pre>
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PUSH BP
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MOV BP, SP
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XCHG BP, [BP]
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</pre>
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This code functions as the 8086/8088 <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> SP instruction on the 80386.
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<p>
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<li>Shift or rotate by more than 31 bits.
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<p>The 80386 masks all shift and rotate counts to the low-order five bits. This MOD 32 operation limits the count to a maximum of 31 bits, thereby limiting the time that interrupt response is delayed while the instruction is executing.
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<p>
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<li>Redundant prefixes.
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<p>The 80386 sets a limit of 15 bytes on instruction length. The only way to violate this limit is by putting redundant prefixes before an instruction. Exception 13 occurs if the limit on instruction length is violated. The 8086/8088 has no instruction length limit.
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<p>
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<li>Operand crossing offset 0 or 65,535.
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<p>On the 8086, an attempt to access a memory operand that crosses offset 65,535 (e.g., <a href="MOV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/MOV.HTM">MOV</a> a word to offset 65,535) or offset 0 (e.g., <a href="PUSH.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSH.HTM">PUSH</a> a word when SP = 1) causes the offset to wrap around modulo 65,536. The 80386 raises an exception in these -- 13 if the segment is a data segment (i.e., if CS, DS, ES, FS, or GS is being used to address the segment), exception 12 if the segment is a stack segment (i.e., if SS is being used).
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<p>
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<li>Sequential execution across offset 65,535.
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<p>On the 8086, if sequential execution of instructions proceeds past offset 65,535, the processor fetches the next instruction byte from offset 0 of the same segment. On the 80386, the processor raises exception 13 in such a case.
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<p>
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<li><a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> is restricted to certain instructions.
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<p>The <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> prefix and its corresponding output signal should only be used to prevent other bus masters from interrupting a data movement operation. The 80386 always asserts the <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> signal during an XCHG instruction with memory (even if the <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> prefix is not used). <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> may only be used with the following 80386 instructions when they update memory: <a href="BTS.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTS.HTM">BTS</a>, <a href="BTR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTR.HTM">BTR</a>, <a href="BTC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/BTC.HTM">BTC</a>, <a href="XCHG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XCHG.HTM">XCHG</a>, <a href="ADD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADD.HTM">ADD</a>, <a href="ADC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/ADC.HTM">ADC</a>, <a href="SUB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SUB.HTM">SUB</a>, <a href="SBB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/SBB.HTM">SBB</a>, <a href="INC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INC.HTM">INC</a>, <a href="DEC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/DEC.HTM">DEC</a>, <a href="AND.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/AND.HTM">AND</a>, <a href="OR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OR.HTM">OR</a>, <a href="XOR.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/XOR.HTM">XOR</a>, <a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM">NOT</a>, and <a href="NEG.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NEG.HTM">NEG</a>. An undefined-opcode exception (interrupt 6) results from using <a href="LOCK.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/LOCK.HTM">LOCK</a> before any other instruction.
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<p>
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<li>Single-stepping external interrupt handlers.
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<p>The priority of the 80386 single-step exception is different from that of the 8086/8088. The change prevents an external interrupt handler from being single-stepped if the interrupt occurs while a program is being single-stepped. The 80386 single-step exception has higher priority that any external interrupt. The 80386 will still single-step through an interrupt handler invoked by the <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> instructions or by an exception.
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<p>
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<li><a href="IDIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IDIV.HTM">IDIV</a> exceptions for quotients of 80H or 8000H.
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<p>The 80386 can generate the largest negative number as a quotient for the <a href="IDIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IDIV.HTM">IDIV</a> instruction. The 8086/8088 causes exception zero instead.
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<p>
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<li>Flags in stack.
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<p>The setting of the flags stored by <a href="PUSHF.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PUSHF.HTM">PUSHF</a>, by interrupts, and by exceptions is different from that stored by the 8086 in bit positions 12 through 15. On the 8086 these bits are stored as ones, but in 80386 real-address mode bit 15 is always zero, and bits 14 through 12 reflect the last value loaded into them.
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<p>
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<li>NMI interrupting NMI handlers.
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<p>After an NMI is recognized on the 80386, the NMI interrupt is masked until an <a href="IRET.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/IRET.HTM">IRET</a> instruction is executed.
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<p>
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<li>Coprocessor errors vector to interrupt 16.
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<p>Any 80386 system with a coprocessor must use interrupt vector 16 for the coprocessor error exception. If an 8086/8088 system uses another vector for the 8087 interrupt, both vectors should point to the coprocessor-error exception handler.
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<p>
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<li>Numeric exception handlers should allow prefixes.
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<p>On the 80386, the value of CS:IP saved for coprocessor exceptions points at any prefixes before an ESC instruction. On 8086/8088 systems, the saved CS:IP points to the ESC instruction.
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<p>
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<li>Coprocessor does not use interrupt controller.
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<p>The coprocessor error signal to the 80386 does not pass through an interrupt controller (an 8087 <a href="INT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/INT.HTM">INT</a> signal does). Some instructions in a coprocessor error handler may need to be deleted if they deal with the interrupt controller.
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<p>
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<li>Six new interrupt vectors.
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<p>The 80386 adds six exceptions that arise only if the 8086 program has a hidden bug. It is recommended that exception handlers be added that treat these exceptions as invalid operations. This additional software does not significantly affect the existing 8086 software because the interrupts do not normally occur. These interrupt identifiers should not already have been used by the 8086 software, because they are in the range reserved by Intel. Table 14-2 describes the new 80386 exceptions.
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<p>
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<li>One megabyte wraparound.
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<p>The 80386 does not wrap addresses at 1 megabyte in real-address mode. On members of the 8086 family, it possible to specify addresses greater than one megabyte. For example, with a selector value 0FFFFH and an offset of 0FFFFH, the effective address would be 10FFEFH (1 Mbyte + 65519). The 8086, which can form adresses only up to 20 bits long, truncates the high-order bit, thereby "wrapping" this address to 0FFEFH. However, the 80386, which can form addresses up to 32 bits long does not truncate such an address.
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</ol>
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<pre>
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Table 14-1. 80386 Real-Address Mode Exceptions
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Description Interrupt Function that Can Return Address
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Number Generate the Exception Points to Faulting
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Instruction
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Divide error 0 DIV, IDIV YES
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Debug exceptions 1 All
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Some debug exceptions point to the faulting instruction, others to the
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next instruction. The exception handler can determine which has occurred by
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examining DR6.
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Breakpoint 3 INT NO
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Overflow 4 INTO NO
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Bounds check 5 BOUND YES
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Invalid opcode 6 Any undefined opcode or LOCK YES
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used with wrong instruction
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Coprocessor not available 7 ESC or WAIT YES
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Interrupt table limit too small 8 INT vector is not within IDTR YES
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limit
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Reserved 9-12
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Stack fault 12 Memory operand crosses offset YES
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0 or 0FFFFH
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Pseudo-protection exception 13 Memory operand crosses offset YES
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0FFFFH or attempt to execute
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past offset 0FFFFH or
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instruction longer than 15
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bytes
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Reserved 14,15
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Coprocessor error 16 ESC or WAIT YES
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Coprocessor errors are reported on the first ESC or WAIT instruction
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after the ESC instruction that caused the error.
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Two-byte SW interrupt 0-255 INT n NO
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</pre>
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<pre>
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Table 14-2. New 80386 Exceptions
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Interrupt Function
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Identifier
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5 A BOUND instruction was executed with a register value outside
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the limit values.
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6 An undefined opcode was encountered or LOCK was used improperly
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before an instruction to which it does not apply.
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7 The EM bit in the MSW is set when an ESC instruction was
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encountered. This exception also occurs on a WAIT instruction
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if TS is set.
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8 An exception or interrupt has vectored to an interrupt table
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entry beyond the interrupt table limit in IDTR. This can occur
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only if the LIDT instruction has changed the limit from the
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default value of 3FFH, which is enough for all 256 interrupt
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IDs.
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12 Operand crosses extremes of stack segment, e.g., MOV operation
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at offset 0FFFFH or push with SP=1 during PUSH, CALL, or INT.
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13 Operand crosses extremes of a segment other than a stack
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segment; or sequential instruction execution attempts to
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proceed beyond offset 0FFFFH; or an instruction is longer than
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15 bytes (including prefixes).
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</pre>
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<p>
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<hr>
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<p><b>up:</b> <a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a><br>
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<b>prev:</b> <a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a><br>
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<b>next:</b> <a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a>
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</body>
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