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160 lines
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<title>80386 Programmer's Reference Manual -- Table of Contents</title>
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<h1>Intel 80386 Reference Programmer's Manual<br>
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Table of Contents
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<h3><a href="C01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C01.HTM">Chapter 1 -- Introduction to the 80386</a></h3>
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<ul>
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<li><a href="S01_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_01.HTM">1.1 Organization of This Manual</a>
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<li><a href="S01_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_02.HTM">1.2 Related Literature</a>
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<li><a href="S01_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S01_03.HTM">1.3 Notational Conventions</a>
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</ul>
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<h2><a href="PI.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PI.HTM">Part I Applications Programming</a></h2>
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<h3><a href="C02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C02.HTM">Chapter 2 -- Basic Programming Model</a></h3>
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<ul>
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<li><a href="S02_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_01.HTM">2.1 Memory Organization and Segmentation</a><br>
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<li><a href="S02_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_02.HTM">2.2 Data Types</a><br>
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<li><a href="S02_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_03.HTM">2.3 Registers</a><br>
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<li><a href="S02_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_04.HTM">2.4 Instruction Format</a><br>
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<li><a href="S02_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_05.HTM">2.5 Operand Selection</a><br>
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<li><a href="S02_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S02_06.HTM">2.6 Interrupts and Exceptions</a>
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</ul>
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<h3><a href="C03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C03.HTM">Chapter 3 -- Applications Instruction Set</a></h3>
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<ul>
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<li><a href="S03_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_01.HTM">3.1 Data Movement Instructions</a><br>
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<li><a href="S03_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_02.HTM">3.2 Binary Arithmetic Instructions</a><br>
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<li><a href="S03_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_03.HTM">3.3 Decimal Arithmetic Instructions</a><br>
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<li><a href="S03_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_04.HTM">3.4 Logical Instructions</a><br>
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<li><a href="S03_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_05.HTM">3.5 Control Transfer Instructions</a><br>
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<li><a href="S03_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_06.HTM">3.6 String and Character Translation Instructions</a><br>
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<li><a href="S03_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_07.HTM">3.7 Instructions for Block-Structured Languages</a><br>
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<li><a href="S03_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_08.HTM">3.8 Flag Control Instructions</a><br>
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<li><a href="S03_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_09.HTM">3.9 Coprocessor Interface Instructions</a><br>
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<li><a href="S03_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_10.HTM">3.10 Segment Register Instructions</a><br>
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<li><a href="S03_11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S03_11.HTM">3.11 Miscellaneous Instructions</a>
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</ul>
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<h2><a href="PII.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PII.HTM">Part II Systems Programming</a></h2>
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<h3><a href="C04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C04.HTM">Chapter 4 -- Systems Architecture</a></h3>
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<ul>
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<li><a href="S04_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_01.HTM">4.1 Systems Registers</a><br>
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<li><a href="S04_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S04_02.HTM">4.2 Systems Instructions</a>
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</ul>
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<h3><a href="C05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C05.HTM">Chapter 5 -- Memory Management</a></h3>
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<ul>
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<li><a href="S05_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_01.HTM">5.1 Segment Translation</a><br>
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<li><a href="S05_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_02.HTM">5.2 Page Translation</a><br>
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<li><a href="S05_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S05_03.HTM">5.3 Combining Segment and Page Translation</a>
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</ul>
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<h3><a href="C06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C06.HTM">Chapter 6 -- Protection</a></h3>
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<ul>
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<li><a href="S06_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_01.HTM">6.1 Why Protection?</a><br>
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<li><a href="S06_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_02.HTM">6.2 Overview of 80386 Protection Mechanisms</a><br>
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<li><a href="S06_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_03.HTM">6.3 Segment-Level Protection</a><br>
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<li><a href="S06_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_04.HTM">6.4 Page-Level Protection</a><br>
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<li><a href="S06_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S06_05.HTM">6.5 Combining Page and Segment Protection</a>
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</ul>
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<h3><a href="C07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C07.HTM">Chapter 7 -- Multitasking</a></h3>
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<ul>
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<li><a href="S07_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_01.HTM">7.1 Task State Segment</a><br>
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<li><a href="S07_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_02.HTM">7.2 TSS Descriptor</a><br>
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<li><a href="S07_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_03.HTM">7.3 Task Register</a><br>
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<li><a href="S07_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_04.HTM">7.4 Task Gate Descriptor</a><br>
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<li><a href="S07_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_05.HTM">7.5 Task Switching</a><br>
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<li><a href="S07_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_06.HTM">7.6 Task Linking</a><br>
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<li><a href="S07_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S07_07.HTM">7.7 Task Address Space</a>
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</ul>
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<h3><a href="C08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C08.HTM">Chapter 8 -- Input/Output</a></h3>
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<ul>
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<li><a href="S08_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_01.HTM">8.1 I/O Addressing</a><br>
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<li><a href="S08_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_02.HTM">8.2 I/O Instructions</a><br>
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<li><a href="S08_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S08_03.HTM">8.3 Protection and I/O</a>
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</ul>
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<h3><a href="C09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C09.HTM">Chapter 9 -- Exceptions and Interrupts</a></h3>
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<ul>
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<li><a href="S09_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_01.HTM">9.1 Identifying Interrupts</a><br>
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<li><a href="S09_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_02.HTM">9.2 Enabling and Disabling Interrupts</a><br>
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<li><a href="S09_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_03.HTM">9.3 Priority Among Simultaneous Interrupts and Exceptions</a><br>
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<li><a href="S09_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_04.HTM">9.4 Interrupt Descriptor Table</a><br>
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<li><a href="S09_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_05.HTM">9.5 IDT Descriptors</a><br>
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<li><a href="S09_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_06.HTM">9.6 Interrupt Tasks and Interrupt Procedures</a><br>
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<li><a href="S09_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_07.HTM">9.7 Error Code</a><br>
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<li><a href="S09_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_08.HTM">9.8 Exception Conditions</a><br>
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<li><a href="S09_09.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_09.HTM">9.9 Exception Summary</a><br>
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<li><a href="S09_10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S09_10.HTM">9.10 Error Code Summary</a>
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</ul>
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<h3><a href="C10.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C10.HTM">Chapter 10 -- Initialization</a></h3>
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<ul>
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<li><a href="S10_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_01.HTM">10.1 Processor State After Reset</a><br>
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<li><a href="S10_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_02.HTM">10.2 Software Initialization for Real-Address Mode</a><br>
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<li><a href="S10_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_03.HTM">10.3 Switching to Protected Mode</a><br>
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<li><a href="S10_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_04.HTM">10.4 Software Initialization for Protected Mode</a><br>
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<li><a href="S10_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_05.HTM">10.5 Initialization Example</a><br>
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<li><a href="S10_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S10_06.HTM">10.6 TLB Testing</a>
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</ul>
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<h3><a href="C11.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C11.HTM">Chapter 11 -- Coprocessing and Multiprocessing</a></h3>
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<ul>
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<li><a href="S11_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_01.HTM">11.1 Coprocessing</a><br>
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<li><a href="S11_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S11_02.HTM">11.2 General Multiprocessing</a>
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</ul>
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<h3><a href="C12.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C12.HTM">Chapter 12 -- Debugging</a></h3>
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<ul>
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<li><a href="S12_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_01.HTM">12.1 Debugging Features of the Architecture</a><br>
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<li><a href="S12_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_02.HTM">12.2 Debug Registers</a><br>
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<li><a href="S12_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S12_03.HTM">12.3 Debug Exceptions</a>
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</ul>
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<h2><a href="PIII.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PIII.HTM">Part III Compatibility</a></h2>
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<h3><a href="C13.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C13.HTM">Chapter 13 -- Executing 80286 Protected-Mode Code</a></h3>
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<ul>
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<li><a href="S13_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_01.HTM">13.1 80286 Code Executes as a Subset of the 80386</a>
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<li><a href="S13_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_02.HTM">13.2 Two ways to Execute 80286 Tasks</a><br>
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<li><a href="S13_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S13_03.HTM">13.3 Differences From 80286</a>
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</ul>
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<h3><a href="C14.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C14.HTM">Chapter 14 -- 80386 Real-Address Mode</a></h3>
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<ul>
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<li><a href="S14_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_01.HTM">14.1 Physical Address Formation</a><br>
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<li><a href="S14_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_02.HTM">14.2 Registers and Instructions</a><br>
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<li><a href="S14_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_03.HTM">14.3 Interrupt and Exception Handling</a><br>
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<li><a href="S14_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_04.HTM">14.4 Entering and Leaving Real-Address Mode</a><br>
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<li><a href="S14_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_05.HTM">14.5 Switching Back to Real-Address Mode</a><br>
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<li><a href="S14_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_06.HTM">14.6 Real-Address Mode Exceptions</a><br>
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<li><a href="S14_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_07.HTM">14.7 Differences From 8086</a><br>
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<li><a href="S14_08.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S14_08.HTM">14.8 Differences From 80286 Real-Address Mode</a>
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</ul>
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<h3><a href="C15.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C15.HTM">Chapter 15 -- Virtual 8086 Mode</a></h3>
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<ul>
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<li><a href="S15_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_01.HTM">15.1 Executing 8086 Code</a><br>
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<li><a href="S15_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_02.HTM">15.2 Structure of a V86 Task</a><br>
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<li><a href="S15_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_03.HTM">15.3 Entering and Leaving V86 Mode</a><br>
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<li><a href="S15_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_04.HTM">15.4 Additional Sensitive Instructions</a><br>
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<li><a href="S15_05.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_05.HTM">15.5 Virtual I/O</a><br>
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<li><a href="S15_06.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_06.HTM">15.6 Differences From 8086</a><br>
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<li><a href="S15_07.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S15_07.HTM">15.7 Differences From 80286 Real-Address Mode</a>
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</ul>
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<h3><a href="C16.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C16.HTM">Chapter 16 -- Mixing 16-Bit and 32 Bit Code</a></h3>
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<ul>
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<li><a href="S16_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_01.HTM">16.1 How the 80386 Implements 16-Bit and 32-Bit Features</a><br>
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<li><a href="S16_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_02.HTM">16.2 Mixing 32-Bit and 16-Bit Operations</a><br>
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<li><a href="S16_03.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_03.HTM">16.3 Sharing Data Segments Among Mixed Code Segments</a>
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<li><a href="S16_04.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S16_04.HTM">16.4 Transferring Control Among Mixed Code Segments></a>
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</ul>
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<h2><a href="PIV.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/PIV.HTM">Part IV Instructions Set</a></h2>
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<h3><a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a></h3>
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<ul>
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<li><a href="S17_01.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_01.HTM">17.1 Operand-Size and Address-Size Attributes</a>
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<li><a href="S17_02.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/S17_02.HTM">17.2 Instruction Format</a>
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</ul>
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<h2><a href="APP.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APP.HTM">Appendices</a></h2>
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<ul>
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<li><a href="APPA.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPA.HTM">Appendix A -- Opcode Map</a><br>
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<li><a href="APPB.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPB.HTM">Appendix B -- Complete Flag Cross-Reference</a><br>
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<li><a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C -- Status Flag Summary</a><br>
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<li><a href="APPD.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPD.HTM">Appendix D -- Condition Codes</a>
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</ul>
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</body>
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