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284 lines
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<!-- This HTML file has been created by texi2html 1.52
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from ../texi/as.texinfo on 24 April 1999 -->
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<TITLE>Using as - MIPS Dependent Features</TITLE>
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</HEAD>
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<BODY>
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Go to the <A HREF="as_1.html">first</A>, <A HREF="as_18.html">previous</A>, <A HREF="as_20.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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<P><HR><P>
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<H1><A NAME="SEC223" HREF="as_toc.html#TOC223">MIPS Dependent Features</A></H1>
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<P>
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<A NAME="IDX713"></A>
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GNU <CODE>as</CODE> for MIPS architectures supports several
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different MIPS processors, and MIPS ISA levels I through IV. For
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information about the MIPS instruction set, see <CITE>MIPS RISC
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Architecture</CITE>, by Kane and Heindrich (Prentice-Hall). For an overview
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of MIPS assembly conventions, see "Appendix D: Assembly Language
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Programming" in the same work.
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</P>
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<H2><A NAME="SEC224" HREF="as_toc.html#TOC224">Assembler options</A></H2>
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<P>
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The MIPS configurations of GNU <CODE>as</CODE> support these
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special options:
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</P>
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<DL COMPACT>
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<DT><CODE>-G <VAR>num</VAR></CODE>
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<DD>
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<A NAME="IDX714"></A>
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This option sets the largest size of an object that can be referenced
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implicitly with the <CODE>gp</CODE> register. It is only accepted for targets
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that use ECOFF format. The default value is 8.
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<A NAME="IDX715"></A>
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<A NAME="IDX716"></A>
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<A NAME="IDX717"></A>
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<A NAME="IDX718"></A>
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<A NAME="IDX719"></A>
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<A NAME="IDX720"></A>
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<DT><CODE>-EB</CODE>
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<DD>
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<DT><CODE>-EL</CODE>
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<DD>
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Any MIPS configuration of <CODE>as</CODE> can select big-endian or
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little-endian output at run time (unlike the other GNU development
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tools, which must be configured for one or the other). Use <SAMP>`-EB'</SAMP>
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to select big-endian output, and <SAMP>`-EL'</SAMP> for little-endian.
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<A NAME="IDX721"></A>
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<DT><CODE>-mips1</CODE>
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<DD>
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<DT><CODE>-mips2</CODE>
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<DD>
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<DT><CODE>-mips3</CODE>
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<DD>
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<DT><CODE>-mips4</CODE>
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<DD>
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Generate code for a particular MIPS Instruction Set Architecture level.
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<SAMP>`-mips1'</SAMP> corresponds to the R2000 and R3000 processors,
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<SAMP>`-mips2'</SAMP> to the R6000 processor, <SAMP>`-mips3'</SAMP> to the
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R4000 processor, and <SAMP>`-mips4'</SAMP> to the R8000 and
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R10000 processors. You can also switch instruction sets during the
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assembly; see section <A HREF="as_19.html#SEC227">Directives to override the ISA level</A>.
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<DT><CODE>-mips16</CODE>
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<DD>
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<DT><CODE>-no-mips16</CODE>
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<DD>
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Generate code for the MIPS 16 processor. This is equivalent to putting
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<SAMP>`.set mips16'</SAMP> at the start of the assembly file. <SAMP>`-no-mips16'</SAMP>
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turns off this option.
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<DT><CODE>-m4650</CODE>
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<DD>
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<DT><CODE>-no-m4650</CODE>
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<DD>
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Generate code for the MIPS R4650 chip. This tells the assembler to accept
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the <SAMP>`mad'</SAMP> and <SAMP>`madu'</SAMP> instruction, and to not schedule <SAMP>`nop'</SAMP>
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instructions around accesses to the <SAMP>`HI'</SAMP> and <SAMP>`LO'</SAMP> registers.
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<SAMP>`-no-m4650'</SAMP> turns off this option.
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<DT><CODE>-m4010</CODE>
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<DD>
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<DT><CODE>-no-m4010</CODE>
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<DD>
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Generate code for the LSI R4010 chip. This tells the assembler to
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accept the R4010 specific instructions (<SAMP>`addciu'</SAMP>, <SAMP>`ffc'</SAMP>,
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etc.), and to not schedule <SAMP>`nop'</SAMP> instructions around accesses to
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the <SAMP>`HI'</SAMP> and <SAMP>`LO'</SAMP> registers. <SAMP>`-no-m4010'</SAMP> turns off this
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option.
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<DT><CODE>-mcpu=<VAR>CPU</VAR></CODE>
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<DD>
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Generate code for a particular MIPS cpu. This has little effect on the
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assembler, but it is passed by <CODE>gcc</CODE>.
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<A NAME="IDX722"></A>
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<DT><CODE>-nocpp</CODE>
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<DD>
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This option is ignored. It is accepted for command-line compatibility with
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other assemblers, which use it to turn off C style preprocessing. With
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GNU <CODE>as</CODE>, there is no need for <SAMP>`-nocpp'</SAMP>, because the
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GNU assembler itself never runs the C preprocessor.
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<DT><CODE>--trap</CODE>
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<DD>
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<DT><CODE>--no-break</CODE>
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<DD>
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<CODE>as</CODE> automatically macro expands certain division and
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multiplication instructions to check for overflow and division by zero. This
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option causes <CODE>as</CODE> to generate code to take a trap exception
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rather than a break exception when an error is detected. The trap instructions
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are only supported at Instruction Set Architecture level 2 and higher.
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<DT><CODE>--break</CODE>
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<DD>
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<DT><CODE>--no-trap</CODE>
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<DD>
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Generate code to take a break exception rather than a trap exception when an
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error is detected. This is the default.
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</DL>
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<H2><A NAME="SEC225" HREF="as_toc.html#TOC225">MIPS ECOFF object code</A></H2>
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<P>
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<A NAME="IDX723"></A>
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<A NAME="IDX724"></A>
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Assembling for a MIPS ECOFF target supports some additional sections
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besides the usual <CODE>.text</CODE>, <CODE>.data</CODE> and <CODE>.bss</CODE>. The
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additional sections are <CODE>.rdata</CODE>, used for read-only data,
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<CODE>.sdata</CODE>, used for small data, and <CODE>.sbss</CODE>, used for small
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common objects.
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</P>
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<P>
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<A NAME="IDX725"></A>
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<A NAME="IDX726"></A>
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When assembling for ECOFF, the assembler uses the <CODE>$gp</CODE> (<CODE>$28</CODE>)
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register to form the address of a "small object". Any object in the
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<CODE>.sdata</CODE> or <CODE>.sbss</CODE> sections is considered "small" in this sense.
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For external objects, or for objects in the <CODE>.bss</CODE> section, you can use
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the <CODE>gcc</CODE> <SAMP>`-G'</SAMP> option to control the size of objects addressed via
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<CODE>$gp</CODE>; the default value is 8, meaning that a reference to any object
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eight bytes or smaller uses <CODE>$gp</CODE>. Passing <SAMP>`-G 0'</SAMP> to
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<CODE>as</CODE> prevents it from using the <CODE>$gp</CODE> register on the basis
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of object size (but the assembler uses <CODE>$gp</CODE> for objects in <CODE>.sdata</CODE>
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or <CODE>sbss</CODE> in any case). The size of an object in the <CODE>.bss</CODE> section
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is set by the <CODE>.comm</CODE> or <CODE>.lcomm</CODE> directive that defines it. The
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size of an external object may be set with the <CODE>.extern</CODE> directive. For
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example, <SAMP>`.extern sym,4'</SAMP> declares that the object at <CODE>sym</CODE> is 4 bytes
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in length, whie leaving <CODE>sym</CODE> otherwise undefined.
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</P>
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<P>
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Using small ECOFF objects requires linker support, and assumes that the
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<CODE>$gp</CODE> register is correctly initialized (normally done automatically by
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the startup code). MIPS ECOFF assembly code must not modify the
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<CODE>$gp</CODE> register.
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</P>
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<H2><A NAME="SEC226" HREF="as_toc.html#TOC226">Directives for debugging information</A></H2>
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<P>
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<A NAME="IDX727"></A>
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MIPS ECOFF <CODE>as</CODE> supports several directives used for
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generating debugging information which are not support by traditional MIPS
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assemblers. These are <CODE>.def</CODE>, <CODE>.endef</CODE>, <CODE>.dim</CODE>, <CODE>.file</CODE>,
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<CODE>.scl</CODE>, <CODE>.size</CODE>, <CODE>.tag</CODE>, <CODE>.type</CODE>, <CODE>.val</CODE>,
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<CODE>.stabd</CODE>, <CODE>.stabn</CODE>, and <CODE>.stabs</CODE>. The debugging information
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generated by the three <CODE>.stab</CODE> directives can only be read by GDB,
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not by traditional MIPS debuggers (this enhancement is required to fully
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support C++ debugging). These directives are primarily used by compilers, not
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assembly language programmers!
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</P>
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<H2><A NAME="SEC227" HREF="as_toc.html#TOC227">Directives to override the ISA level</A></H2>
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<P>
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<A NAME="IDX728"></A>
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<A NAME="IDX729"></A>
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GNU <CODE>as</CODE> supports an additional directive to change
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the MIPS Instruction Set Architecture level on the fly: <CODE>.set
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mips<VAR>n</VAR></CODE>. <VAR>n</VAR> should be a number from 0 to 4. A value from 1
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to 4 makes the assembler accept instructions for the corresponding
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ISA level, from that point on in the assembly. <CODE>.set
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mips<VAR>n</VAR></CODE> affects not only which instructions are permitted, but also
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how certain macros are expanded. <CODE>.set mips0</CODE> restores the
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ISA level to its original level: either the level you selected with
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command line options, or the default for your configuration. You can
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use this feature to permit specific R4000 instructions while
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assembling in 32 bit mode. Use this directive with care!
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</P>
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<P>
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The directive <SAMP>`.set mips16'</SAMP> puts the assembler into MIPS 16 mode,
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in which it will assemble instructions for the MIPS 16 processor. Use
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<SAMP>`.set nomips16'</SAMP> to return to normal 32 bit mode.
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</P>
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<P>
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Traditional MIPS assemblers do not support this directive.
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</P>
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<H2><A NAME="SEC228" HREF="as_toc.html#TOC228">Directives for extending MIPS 16 bit instructions</A></H2>
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<P>
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<A NAME="IDX730"></A>
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<A NAME="IDX731"></A>
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By default, MIPS 16 instructions are automatically extended to 32 bits
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when necessary. The directive <SAMP>`.set noautoextend'</SAMP> will turn this
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off. When <SAMP>`.set noautoextend'</SAMP> is in effect, any 32 bit instruction
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must be explicitly extended with the <SAMP>`.e'</SAMP> modifier (e.g.,
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<SAMP>`li.e $4,1000'</SAMP>). The directive <SAMP>`.set autoextend'</SAMP> may be used
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to once again automatically extend instructions when necessary.
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</P>
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<P>
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This directive is only meaningful when in MIPS 16 mode. Traditional
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MIPS assemblers do not support this directive.
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</P>
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<H2><A NAME="SEC229" HREF="as_toc.html#TOC229">Directive to mark data as an instruction</A></H2>
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<P>
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<A NAME="IDX732"></A>
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The <CODE>.insn</CODE> directive tells <CODE>as</CODE> that the following
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data is actually instructions. This makes a difference in MIPS 16 mode:
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when loading the address of a label which precedes instructions,
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<CODE>as</CODE> automatically adds 1 to the value, so that jumping to
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the loaded address will do the right thing.
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</P>
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<H2><A NAME="SEC230" HREF="as_toc.html#TOC230">Directives to save and restore options</A></H2>
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<P>
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<A NAME="IDX733"></A>
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<A NAME="IDX734"></A>
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<A NAME="IDX735"></A>
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The directives <CODE>.set push</CODE> and <CODE>.set pop</CODE> may be used to save
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and restore the current settings for all the options which are
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controlled by <CODE>.set</CODE>. The <CODE>.set push</CODE> directive saves the
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current settings on a stack. The <CODE>.set pop</CODE> directive pops the
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stack and restores the settings.
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</P>
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<P>
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These directives can be useful inside an macro which must change an
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option such as the ISA level or instruction reordering but does not want
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to change the state of the code which invoked the macro.
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</P>
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<P>
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Traditional MIPS assemblers do not support these directives.
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</P>
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<P><HR><P>
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Go to the <A HREF="as_1.html">first</A>, <A HREF="as_18.html">previous</A>, <A HREF="as_20.html">next</A>, <A HREF="as_27.html">last</A> section, <A HREF="as_toc.html">table of contents</A>.
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</BODY>
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</HTML>
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