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<TITLE>Int 06
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<META NAME="Description" CONTENT="
Int 06 - CPU-generated (80186+) - INVALID OPCODE -
Desc: this interrupt is generated when the CPU attempts to execute an
invalid opcode (most protected-mode instructions are considered
invalid in real mode) or a BOUND, LDS, LES, or LIDT instruction
which specifies a register rather than a memory address
Notes: return address points to beginning of invalid instruction
with proper programming, this interrupt may be used to emulate
instructions which do not exist; many 386 BIOSes emulate the 80286
undocumented LOADALL instruction which was removed from the 80386+
generated by the 80386+ when the LOCK prefix is used with instructions
other than BTS, BTR, BTC, XCHG, XADD (486), CMPXCHG (486), INC, DEC,
">
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<h2>Int 06
</h2>
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<h3><font color=#C00040>CPU-generated (80186+) - INVALID OPCODE</font></h3>
<p><b>Desc:</b>
This interrupt is generated when the CPU attempts to execute an
invalid opcode (most protected-mode instructions are considered
invalid in real mode) or a BOUND, LDS, LES, or LIDT instruction
which specifies a register rather than a memory address
<p><b>Notes:</b>
Return address points to beginning of invalid instruction.
With proper programming, this interrupt may be used to emulate
instructions which do not exist; many 386 BIOSes emulate the 80286
undocumented LOADALL instruction which was removed from the 80386+.
Generated by the 80386+ when the LOCK prefix is used with instructions
other than BTS, BTR, BTC, XCHG, XADD (486), CMPXCHG (486), INC, DEC,
NOT, NEG, ADD, ADC, SUB, SBB, AND, OR, or XOR, or any instruction
not accessing memory.
<p><b>See Also:</b>
<a href="rb-0056.htm" tppabs="http://www.ctyme.com/intr/rb-0056.htm">INT 0C"CPU"</a> - <a href="rb-0061.htm" tppabs="http://www.ctyme.com/intr/rb-0061.htm">INT 0D"CPU"</a>
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CPU-Generated</a>
- <a href="int-06.htm" tppabs="http://www.ctyme.com/intr/int-06.htm">
Int 06h</a>
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C</a>
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