1049 lines
40 KiB
HTML
1049 lines
40 KiB
HTML
<HTML>
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<HEAD>
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<TITLE>Int 1A/AX=B10Ah/SF=1045h
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</TITLE>
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<META NAME="Description" CONTENT="
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Int 1A/AX=B10Ah/SF=1045h - PCI BIOS v2.0c+ - READ CONFIGURATION DWORD (OPTi devices) -
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AX = B10Ah subfn 1045h
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh) (see #00878)
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Return: CF clear if successful
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ECX = dword read
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CF set on error
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AH = status (00h,87h) (see #00729)
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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">
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<META NAME="robots" CONTENT="none">
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</HEAD>
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<BODY BGCOLOR="#FFD0A0">
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<center>
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<h2>Int 1A/AX=B10Ah/SF=1045h
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</h2>
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</center><p>
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<table border=1 cellpadding=3 cellspacing=1>
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<td>
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<a href="rb-2382.htm" tppabs="http://www.ctyme.com/intr/rb-2382.htm">
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<img src="lhome.gif" tppabs="http://graphics.ctyme.com/gif/lhome.gif" border=0 alt=Ralf Brown Page></a>
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<td><a href="int.htm" tppabs="http://www.ctyme.com/intr/int.htm">Interrups</a></td>
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<td><a href="cat.htm" tppabs="http://www.ctyme.com/intr/cat.htm">Categories</a></td>
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<td><a href="alpha.htm" tppabs="http://www.ctyme.com/intr/alpha.htm">Contents</a></td>
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</td></table><p>
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<p><img src="rbline.gif" tppabs="http://graphics.ctyme.com/gif/rbline.gif" width="100%" alt="------"><p>
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<h3><font color=#C00040>PCI BIOS v2.0c+ - READ CONFIGURATION DWORD (OPTi devices)</font></h3>
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<PRE>
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AX = B10Ah subfn 1045h
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh) <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a><br>
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<p><b>Return:</b><br>CF clear if successful
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ECX = dword read
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CF set on error
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AH = status (00h,87h) <a href="rb-2371.htm#Table729" tppabs="http://www.ctyme.com/intr/rb-2371.htm#Table729">(see #00729)</a>
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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</PRE>
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<p><b>Notes:</b>
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This function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call.
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The meanings of BL and BH on entry were exchanged between the initial
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drafts of the specification and final implementation
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<p><b>See Also:</b>
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<a href="rb-2377.htm" tppabs="http://www.ctyme.com/intr/rb-2377.htm">AX=B10Ah</a> - <a href="rb-2382.htm" tppabs="http://www.ctyme.com/intr/rb-2382.htm">AX=B10Ah/SF=1042h</a> - <a href="rb-2384.htm" tppabs="http://www.ctyme.com/intr/rb-2384.htm">AX=B10Ah/SF=1066h</a>
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<PRE>
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<p>
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Format of PCI Configuration data for OPTi 82C750 Vendetta (device 0):
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<a name=table929></a>
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Offset Size Description (Table 00929)
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00h 64 BYTEs header <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a>
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(vendor ID 1045h, device ID C567h)
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40h DWORD memory control <a href="rb-2383.htm#Table930" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table930">(see #00930)</a>
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44h 6 BYTEs data path control <a href="rb-2383.htm#Table931" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table931">(see #00931)</a>
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4Ah WORD reserved
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4Ch BYTE SDRAM SDRAS/SDCAS mux control <a href="rb-2383.htm#Table932" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table932">(see #00932)</a>
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4Dh BYTE SDRAM select <a href="rb-2383.htm#Table933" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table933">(see #00933)</a>
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4Eh BYTE ECC test / I2C control <a href="rb-2383.htm#Table934" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table934">(see #00934)</a>
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4Fh BYTE ECC test data
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50h DWORD ECC control <a href="rb-2383.htm#Table935" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table935">(see #00935)</a>
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54h WORD SDRAM select <a href="rb-2383.htm#Table936" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table936">(see #00936)</a>
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56h BYTE data path control / EDO X-2-2-2 writes <a href="rb-2383.htm#Table937" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table937">(see #00937)</a>
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57h BYTE reserved
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58h DWORD ECC reporting <a href="rb-2383.htm#Table938" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table938">(see #00938)</a>
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5Ch 164 BYTEs reserved
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</PRE>
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<p><b>See Also:</b>
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#00878 - #00939 - #00965
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) memory control:
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<a name=table930></a>
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Bit(s) Description (Table 00930)
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31-30 reserved
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29 reserved (1)
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28-18 reserved
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17 reserved (1)
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16 HA drive-back during CPU memory access enable
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15-6 PCI video frame buffer write posting hole
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5-4 reserved
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3 PCI bus write post disable
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2 video frame buffer write post (posting enabled if bit 2 = bit 3)
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1 video memory write post(posting enabled if bit 1 = bit 3)
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0 I/O cycle write post enable
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</PRE>
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<p><b>See Also:</b>
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#00929 - #00931
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) data path control:
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<a name=table931></a>
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Bit(s) Description (Table 00931)
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41-47 reserved
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40 DTY pin suspend enable
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39-38 reserved
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37 SDRAM refresh 0 sized bank RAS# disable
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36 SDRAM control signal stepping enable
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35 reserved
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34-32 SDRAM mode.
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000 = normal.
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001 = NOP enable.
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010 = precharge all banks.
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011 = mode register enable.
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100 = CBR cycle enable.
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101-111 = reserved
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31 SDRAM memory read access enable
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30 CPU-to-PCI FIFO clear enable
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29 PCI-to-DRAM FIFO clear enable
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28 CPU-to-DRAM FIFO clear enable
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27 82C750 register write disable
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26-15 reserved
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14 PCI master/ECC generate NMI disable
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13-12 reserved (1)
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11 memory parity checking enable
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10 reserved
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9 CPU DRAM write byte merge enable
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8 MD bus pull-up resistor disable
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7 PCI CPU write 6DW FIFO enable
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6 DRAM PCI read 24DW FIFO enable
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5 DRAM PCI write 24DW FIFO enable
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4 DRAM CPU write 8QW FIFO enable
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3 82C750 memory read access (0 = SDRAM, 1 = reserved)
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2-1 reserved
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0 82C750 memory read access (0 = FP mode, 1 = EDO/SDRAM)
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM SDRAS/SDCAS mux control:
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<a name=table932></a>
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Bit(s) Description (Table 00932)
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7 MCACHE enable
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6 GWE#/BWE# (1)
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5 reserved (read-only)
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4 reserved (1)
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3 BOFF# CPU status latch enable
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2 reserved (1) (SDRAS# & SDCAS#)
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1 reserved (1) (BA1 & BA0)
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0 pin mux.
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0 = RAS4# & RAS5#.
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1 = SDRAS# & SDCAS#
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM select:
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<a name=table933></a>
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Bit(s) Description (Table 00933)
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7-6 reserved
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5 bank 5 enable
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4 bank 4 enable
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3-0 reserved
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) ECC test / I2C control:
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<a name=table934></a>
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Bit(s) Description (Table 00934)
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7 ECC test mode enable
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6 reserved
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5 reserved (1 if SDRAM enabled)
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4 I2C data output read-back (read-only)
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3 I2C clock output read-back (read-only)
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2 I2C data output (refer to file I2C.LST for more details)
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1 I2C clock output
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0 I2C control enable
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</PRE>
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<p><b>See Also:</b>
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#00929 - I2C A0h - #00935
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) ECC control:
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<a name=table935></a>
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Bit(s) Description (Table 00935)
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31-13 upper 19 bits of error address
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12-5 syndrome byte for reported error
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4 non-correctable error
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3 single-bit error
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2 nibble error
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1 ECC error report enable
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0 ECC data path enable
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</PRE>
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<p><b>See Also:</b>
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#00929 - #00934
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) SDRAM select:
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<a name=table936></a>
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Bit(s) Description (Table 00936)
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15 SDWE# stepping enable
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14 reserved (1) (SDRAM)
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13-12 reserved
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11-6 bank 5-0 SDRAM technology.
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0 = 16 Mb.
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1 = 64 Mb
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5-0 bank 5-0 SDRAM timing.
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0 = leadoff 7/6.
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1 = leadoff 8/7
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) data path control / EDO X-2-2-2:
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<a name=table937></a>
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Bit(s) Description (Table 00937)
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7 CPU-to-DRAM FIFO enable
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6 1 CLK CAS enable
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5-0 RAS5#-RAS0# X-2-2-2 write enable.
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(CPU-to-DRAM FIFO, DRAM write post, and cache readaround write must
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be enabled)
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 0) ECC reporting:
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<a name=table938></a>
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Bit(s) Description (Table 00938)
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31-26 reserved
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25-16 single-bit error counter
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15 reserved
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14 delayed write enable
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13-4 single-bit error limit
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3 correctable error reporting (0 = NMI, 1 = SMI)
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2 single-bit error counter enable (disabling resets counter)
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1 error reporting method (0 = NMI, 1 = SMI)
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0 NMI/SMI generate disable
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</PRE>
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<p><b>See Also:</b>
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#00929
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<PRE>
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<p>
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Format of PCI Configuration data for OPTi 82C750 Vendetta (device 1):
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<a name=table939></a>
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Offset Size Description (Table 00939)
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00h 64 BYTEs header <a href="rb-2372.htm#Table824" tppabs="http://www.ctyme.com/intr/rb-2372.htm#Table824">(see #00824)</a>
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(vendor ID 1045h, device ID C568h)
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40h WORD keyboard control <a href="rb-2383.htm#Table940" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table940">(see #00940)</a>
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42h WORD interrupt control <a href="rb-2383.htm#Table941" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table941">(see #00941)</a>
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44h BYTE pin functionality 1 <a href="rb-2383.htm#Table942" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table942">(see #00942)</a>
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45h BYTE reserved
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46h WORD cycle control <a href="rb-2383.htm#Table943" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table943">(see #00943)</a>
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48h WORD pin functionality 2 <a href="rb-2383.htm#Table944" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table944">(see #00944)</a>
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4Ah WORD ROMCS# range control <a href="rb-2383.htm#Table945" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table945">(see #00945)</a>
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4Ch BYTE miscellaneous control 1 <a href="rb-2383.htm#Table946" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table946">(see #00946)</a>
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4Dh BYTE reserved
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4Eh BYTE miscellaneous control 2 <a href="rb-2383.htm#Table947" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table947">(see #00947)</a>
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4Fh BYTE miscellaneous control 3 <a href="rb-2383.htm#Table948" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table948">(see #00948)</a>
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50h WORD interrupt trigger control <a href="rb-2383.htm#Table949" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table949">(see #00949)</a>
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52h WORD interrupt multiplexing control <a href="rb-2383.htm#Table950" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table950">(see #00950)</a>
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54h WORD PCI master control <a href="rb-2383.htm#Table951" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table951">(see #00951)</a>
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56h WORD serial interrupt source <a href="rb-2383.htm#Table952" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table952">(see #00952)</a>
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58h BYTE serial interrupt mode control <a href="rb-2383.htm#Table953" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table953">(see #00953)</a>
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59h BYTE pin functionality 3 <a href="rb-2383.htm#Table954" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table954">(see #00954)</a>
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5Ah WORD distributed DMA master base address
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5Ch BYTE distributed DMA control <a href="rb-2383.htm#Table955" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table955">(see #00955)</a>
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5Dh 3 BYTEs reserved
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60h BYTE USB interrupt control register <a href="rb-2383.htm#Table956" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table956">(see #00956)</a>
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61h BYTE PCI reset control <a href="rb-2383.htm#Table957" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table957">(see #00957)</a>
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62h BYTE emulation control <a href="rb-2383.htm#Table958" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table958">(see #00958)</a>
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63h BYTE PCI retry control <a href="rb-2383.htm#Table959" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table959">(see #00959)</a>
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64h 153 BYTEs reserved
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FDh BYTE SMI control
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FEh BYTE stop grant cycle control
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FFh BYTE host memory parity error
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</PRE>
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<p><b>See Also:</b>
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#00878 - #00929 - #00965
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 1) keyboard control:
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<a name=table940></a>
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Bit(s) Description (Table 00940)
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15 keyboard port read (read-only)
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14 keyboard port write (read-only)
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13 keyboard RESET CPUINIT.
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0 = generate immediately.
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1 = wait for halt
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12 keyboard emulation disable
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11-9 PIRQ3# IRQ generation.
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000 = use interrupt trigger control register (offset 50h).
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001 = IRQ5.
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010-101 = IRQ9-IRQ12.
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110-111 = IRQ14-IRQ15
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8-6 PIRQ2# IRQ generation
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5-3 PIRQ1# IRQ generation
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2-0 PIRQ0# IRQ generation
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</PRE>
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<p><b>See Also:</b>
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#00939 - #00941
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 1) interrupt control:
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<a name=table941></a>
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Bit(s) Description (Table 00941)
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15 ISA IRQ14 blocking enable
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14 ISA IRQ15 blocking enable
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13 DMA/ISA master to preempt PCI master enable
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12 PCI priority is fixed instead of rotating
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11-10 back-to-back ISA I/O delay.
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00 = 3 ATCLKs.
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01 = 12 ATCLKs.
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10 = no delay.
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11 = delay all by 12 ATCLKs
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9 PCI master ISA device access disable
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8 ISA bus control signals for memory access >16M and I/O access >64K
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disable
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7-6 IRQ15-IRQ14 triggering (0 = edge, 1 = level)
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5-2 IRQ12-IRQ9 triggering (0 = edge, 1 = level)
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1 IRQ 5 triggering (0 = edge, 1 = level)
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0 pin AE16 functionality.
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0 = DREQ6.
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1 = EPMI0#
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</PRE>
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<p><b>See Also:</b>
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#00939 - #00940
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<PRE>
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<p>
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Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 1:
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<a name=table942></a>
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Bit(s) Description (Table 00942)
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7-6 pin AC15 functionality.
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00-01 = controlled by bits 1-0.
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10 = DACK7#.
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11 = reserved
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5-4 pin AE15 functionality.
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00-01 = controlled by bits 1-0.
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10 = DACK6#.
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11 = reserved
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3-2 pin AF15 functionality.
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00-01 = controlled by bits 1-0.
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10 = DACK5#.
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11 = reserved
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1-0 DACK group-wise programmable pin functionalities.
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00 = DACK3#-DACK0#.
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01 = DACK7#-DACK5#, DACK3#, DACK1#, DACK0#.
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10 = reserved.
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11 = EDACK2#-EDACK0#, EDACKEN#, PIRQ3#, PIRQ2#
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</PRE>
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<p><b>See Also:</b>
|
|
#00939
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<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) cycle control:
|
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<a name=table943></a>
|
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Bit(s) Description (Table 00943)
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15 ISA bus ROM write enable
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14 hidden refresh enable
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13-12 ATCLK select.
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00 = LCLK/4.
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01 = LCLK/3.
|
|
10 = LCLK/2.
|
|
11 = LCLK
|
|
11 CPU master to PCI slave write.
|
|
0 = 1 LCLK.
|
|
1 = 0 LCLK
|
|
10-8 PCI master to PCI master preempt timer.
|
|
000 = no preempt.
|
|
001 = 260 LCLKs.
|
|
010 = 132 LCLKs.
|
|
011 = 68 LCLKs.
|
|
100 = 36 LCLKs.
|
|
101 = 20 LCLKs.
|
|
110 = 12 LCLKs.
|
|
111 = 5 LCLKs
|
|
7 reserved
|
|
6 XDIR achieve.
|
|
0 = accessing ROM, keyboard controller, RTC.
|
|
1 = accessing ROM, NVRAM
|
|
5 PERR# to SERR# conversion enable
|
|
4 address parity checking enable
|
|
3 target abort SERR# generation enable
|
|
2 fast back-to-back enable
|
|
1 sample point decoding.
|
|
0 = slow.
|
|
1 = subtractive
|
|
0 reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 2:
|
|
<a name=table944></a>
|
|
Bit(s) Description (Table 00944)
|
|
15 pin AF18 functionality (0 = IRQ15, 1 = reserved)
|
|
14-13 pin AE19 functionality (00-01 = IRQ12, 10-11 = reserved)
|
|
12 pin AD20 functionality (0 = IRQ10, 1 = MIRQ10/12)
|
|
11 pin AE21 functionality (0 = IRQ6, 1 = reserved)
|
|
10 pin AD22 functionality (0 = IRQ4, 1 = MIRQ4/6)
|
|
9-8 pin AD16 functionality (00 = DREQ7, 01 = EPMI3#, 1x = reserved)
|
|
7-6 pin AD17 functionality.
|
|
00 = DREQ3.
|
|
01 = DREQ3/7.
|
|
10 = DREQ7.
|
|
11 = reserved
|
|
5-4 pin AD18 functionality.
|
|
00 = DREQ1.
|
|
01 = DREQ1/6.
|
|
10 = DREQ6.
|
|
11 = reserved
|
|
3-2 pin AE18 functionality.
|
|
00 = DREQ0.
|
|
01 = DREQ0/5.
|
|
10 = DREQ5.
|
|
11 = reserved
|
|
1-0 pin T23 functionality (0x = PREQ1#, 1x = reserved)
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) ROMCS# range control:
|
|
<a name=table945></a>
|
|
Bit(s) Description (Table 00945)
|
|
15 FFFF8000h-FFFFFFFFh ROMCS# disable
|
|
14 FFFF0000h-FFFF7FFFh ROMCS# disable
|
|
13 FFFE8000h-FFFEFFFFh ROMCS# enable
|
|
12 FFFE0000h-FFFE7FFFh ROMCS# enable
|
|
11 FFFD8000h-FFFDFFFFh ROMCS# enable
|
|
10 FFFD0000h-FFFD7FFFh ROMCS# enable
|
|
9 FFFC8000h-FFFCFFFFh ROMCS# enable
|
|
8 FFFC0000h-FFFC7FFFh ROMCS# enable
|
|
7 F8000h-FFFFFh ROMCS# disable
|
|
6 F0000h-F7FFFh ROMCS# disable
|
|
5 E8000h-EFFFFh ROMCS# enable
|
|
4 E0000h-E7FFFh ROMCS# enable
|
|
3 D8000h-DFFFFh ROMCS# enable
|
|
2 D0000h-D7FFFh ROMCS# enable
|
|
1 C8000h-CFFFFh ROMCS# enable
|
|
0 C0000h-C7FFFh ROMCS# enable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 1:
|
|
<a name=table946></a>
|
|
Bit(s) Description (Table 00946)
|
|
7-5 reserved
|
|
4 game port/MPU-401 enable
|
|
3 PREQ4#/PGNT4# mux (0 = SDA2/GP3, 1 = PREQ4#/PGNT4#)
|
|
2 DACK5# 1-to-0 transition enable
|
|
1-0 reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00947 - #00948
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 2:
|
|
<a name=table947></a>
|
|
Bit(s) Description (Table 00947)
|
|
7-4 reserved
|
|
3 pipeline byte merge enable
|
|
2 EOP configuration (0 = output, 1 = input)
|
|
1 byte merge enable
|
|
0 ISA master data swap disable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00946 - #00948
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) miscellaneous control 3:
|
|
<a name=table948></a>
|
|
Bit(s) Description (Table 00948)
|
|
7 pin AB15 functionality.
|
|
0 = DACK5#.
|
|
1 = PPWRL+PPWRL2
|
|
6 IDE functionality support enable
|
|
5 reserved (read-only)
|
|
4 ISA bus AT command 1 wait state extension disable
|
|
3-2 reserved
|
|
1 pin AE14 functionality.
|
|
0 = controlled by offset 44h bits 1-0.
|
|
1 = GPCS2#
|
|
0 reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00946 - #00947
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) interrupt trigger control:
|
|
<a name=table949></a>
|
|
Bit(s) Description (Table 00949)
|
|
15 reserved (1)
|
|
14 reserved
|
|
13 pin AD15 functionality (0 = DACK2#, 1 = GPCS2#)
|
|
12-11 reserved
|
|
10 IRQ3 triggering (0 = edge, 1 = level)
|
|
9 IRQ4 triggering (0 = edge, 1 = level)
|
|
8 IRQ7 triggering (0 = edge, 1 = level)
|
|
7-6 IRQ generation when PIRQ3# triggered.
|
|
00 = disable.
|
|
01 = IRQ3.
|
|
10 = IRQ4.
|
|
11 = IRQ7
|
|
5-4 IRQ generation when PIRQ2# triggered.
|
|
00 = disable.
|
|
01 = IRQ3.
|
|
10 = IRQ4.
|
|
11 = IRQ7
|
|
3-2 IRQ generation when PIRQ1# triggered.
|
|
00 = disable.
|
|
01 = IRQ3.
|
|
10 = IRQ4.
|
|
11 = IRQ7
|
|
1-0 IRQ generation when PIRQ0# triggered.
|
|
00 = disable.
|
|
01 = IRQ3.
|
|
10 = IRQ4.
|
|
11 = IRQ7
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00950
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) interrupt multiplexing control:
|
|
<a name=table950></a>
|
|
Bit(s) Description (Table 00950)
|
|
15 pin functionality.
|
|
0 = AE22:IRQ3, AF21:IRQ5, AE21:IRQ6, AD21:IRQ7, AE20:IRQ9, AF19:IRQ11.
|
|
1 = AE22:MIRQ3/5, AF21:MIRQ7/9, AE21:MIRQ11/15,
|
|
AD21:EPMI1#, AE20:EPMI2#, AF19:GMIRQ
|
|
14 pin R22 functionality (0 = PREQ2#, 1 = EPMI0#)
|
|
13 IRQ1 latching enable
|
|
12 IRQ12 latching enable
|
|
11 DACKEN# status (0 = active low, 1 = active high)
|
|
10 system bus owned by external device
|
|
9 flash ROM locking enable
|
|
8 reserved
|
|
7 IRQ6 triggering (0 = edge, 1 = level)
|
|
6-3 IRQ generation when GMIRQ triggered.
|
|
0000 = disabled.
|
|
0001-0010 = reserved.
|
|
0011-0111 = IRQ3-IRQ7.
|
|
1000 = reserved.
|
|
1001-1100 = IRQ9-IRQ12.
|
|
1101 = reserved.
|
|
1110-1111 = IRQ14-IRQ15
|
|
2 reserved (1)
|
|
1 priority scheme enable
|
|
0 concurrent refresh and IDE cycle enable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00949
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) PCI master control:
|
|
<a name=table951></a>
|
|
Bit(s) Description (Table 00951)
|
|
15-12 reserved
|
|
11 interrupt request register recover enable
|
|
10 DMA address and counter (0 = current, 1 = base)
|
|
9 CPU/PCI master access ISA cycle retry enable
|
|
8 CPU-to-PCI cycle AHOLD signal use enable.
|
|
(used only when bit 4 = 1)
|
|
7 PCI master X-1-1-1 write enable
|
|
6 PCI master X-1-1-1 read enable
|
|
5 concurrent PCI master/IDE enable
|
|
4 new AHOLD protocol enable
|
|
3 PCI master non-contiguous byte enable
|
|
2 reserved
|
|
1 simultaneous hardware PMU and IDE function operation enable
|
|
0 ISA refresh disable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) serial interrupt source:
|
|
<a name=table952></a>
|
|
Bit(s) Description (Table 00952)
|
|
15-3 IRQ15-IRQ3 interrupt resource (0 = ISA, 1 = serial interrupt)
|
|
2 SMI#, IOCHK#, PCIRQ3#-PCIRQ0# interrupt resource.
|
|
0 = ISA.
|
|
1 = serial interrupt
|
|
1-0 IRQ1-IRQ0 interrupt resource (0 = ISA, 1 = serial interrupt)
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00953
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) serial interrupt mode control:
|
|
<a name=table953></a>
|
|
Bit(s) Description (Table 00953)
|
|
7-6 serial interrupt control mode.
|
|
00 = continuous.
|
|
01 = idle.
|
|
1x = active
|
|
5 reserved
|
|
4 data frame slot support.
|
|
0 = 17 slots (IRQ15-IRQ3, IRQ1-IRQ0, SMI#, IOCHK#).
|
|
1 = 21 slots (IRQ15-IRQ3, IRQ1-IRQ0, SMI#, IOCHK#, PCIRQ3#-PCIRQ0#)
|
|
3-2 CPU access PCI priority.
|
|
00 = lowest.
|
|
01 = higher after 4 PCI master grants.
|
|
10 = higher after 2 PCI master grants.
|
|
11 = higher after 3 PCI master grants
|
|
1-0 serial interrupt start frame pulse width in continuous/active mode.
|
|
00 = 4/3 CLK.
|
|
01 = 6/5 CLK.
|
|
10 = 8/7 CLK.
|
|
11 = reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - #00952
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) pin functionality 3:
|
|
<a name=table954></a>
|
|
Bit(s) Description (Table 00954)
|
|
7 PCI arbitration time-out mode enable
|
|
6 0 wait state for CPU I/O access enable
|
|
5 SMI output disable
|
|
4 CPU request for PCI bus (0 = enabled, 1 = reserved)
|
|
3 reserved
|
|
2 refresh preemption disable
|
|
1-0 reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) distributed DMA control:
|
|
<a name=table955></a>
|
|
Bit(s) Description (Table 00955)
|
|
7-5 channel 7-5 enable
|
|
4-1 channel 3-0 enable
|
|
0 DDMA enable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) USB interrupt control register:
|
|
<a name=table956></a>
|
|
Bit(s) Description (Table 00956)
|
|
7 reserved
|
|
6-5 buffered DMA control.
|
|
00 = original DMA with old protocol.
|
|
01 = reserved.
|
|
10 = original DMA with PCI master capability.
|
|
11 = buffered DMA enable
|
|
4 reserved
|
|
3-0 IRQ generation when USBIRQ triggered.
|
|
0000 = disabled.
|
|
0001-0010 = reserved.
|
|
0011-0111 = IRQ3-IRQ7.
|
|
1000 = reserved.
|
|
1001-1100 = IRQ9-IRQ12.
|
|
1101 = reserved.
|
|
1110-1111 = IRQ14-IRQ15
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) PCI reset control:
|
|
<a name=table957></a>
|
|
Bit(s) Description (Table 00957)
|
|
7 PCI soft reset generate enable
|
|
6 PCI slave demand mode buffered DMA retry fix enable
|
|
5 IORDY# PCI master delay fix enable
|
|
4 ISA command deassertion IOCHRDY delay.
|
|
0 = <1 ATCLK.
|
|
1 = >=1 ATCLK
|
|
3-2 buffered DMA fix (00 = disable, 11 = enable)
|
|
1 reserved
|
|
0 ISA master synchronization (1)
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) emulation control:
|
|
<a name=table958></a>
|
|
Bit(s) Description (Table 00958)
|
|
7 PCIRST# disable
|
|
6 SDA2 muxed with XDIR (0 = XDIR, 1 = SDA2)
|
|
5 SPKR muxed with MIDI1 (0 = MIDI1, 1 = SPKR)
|
|
4 audio mux (0 = MP7-MP0, DACK)
|
|
3 audio module enable
|
|
2 ATA-33 IDE pin mux scheme (0 = old, 1 = new)
|
|
1 REFRESH priority (0 = high, 1 = lowest)
|
|
0 port 92h emulation disable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939 - PORT 0092h
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (device 1) PCI retry control:
|
|
<a name=table959></a>
|
|
Bit(s) Description (Table 00959)
|
|
7-2 reserved
|
|
1 reserved (1)
|
|
0 ISA slave PCI master retry.
|
|
0 = no change.
|
|
1 = generate BOFF#
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00939
|
|
<PRE>
|
|
<p>
|
|
Format of PCI Configuration data for OPTi 82C750 Vendetta (IDE controller):
|
|
<a name=table960></a>
|
|
Offset Size Description (Table 00960)
|
|
00h 64 BYTEs header <a href="rb-2372.htm#Table824" tppabs="http://www.ctyme.com/intr/rb-2372.htm#Table824">(see #00824)</a>
|
|
(vendor ID 1045h, device ID C621h)
|
|
40h BYTE IDE initialization control <a href="rb-2383.htm#Table961" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table961">(see #00961)</a>
|
|
41h BYTE reserved
|
|
42h BYTE IDE enhanced feature <a href="rb-2383.htm#Table962" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table962">(see #00962)</a>
|
|
43h BYTE IDE enhanced mode <a href="rb-2383.htm#Table963" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table963">(see #00963)</a>
|
|
44h WORD ultra DMA mode select <a href="rb-2383.htm#Table964" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table964">(see #00964)</a>
|
|
46h 186 BYTEs reserved
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE initialization control:
|
|
<a name=table961></a>
|
|
Bit(s) Description (Table 00961)
|
|
7-6 bus master IDE PCI bus request when FIFO filled with.
|
|
00 = 32 bytes (early request disabled).
|
|
01 = 30 bytes.
|
|
10 = 28 bytes.
|
|
11 = 26 bytes
|
|
5 reserved (1)
|
|
4 reserved
|
|
3 secondary IDE disable
|
|
2 I/O addresses relocatable
|
|
1-0 IDE device default cycle time.
|
|
00 = >=600ns (PIO mode 0).
|
|
01 = >=383ns (PIO mode 2).
|
|
10 = >=240ns (PIO mode 1).
|
|
11 = >=180ns (PIO mode 3)
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00960
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE enhanced feature:
|
|
<a name=table962></a>
|
|
Bit(s) Description (Table 00962)
|
|
7 reserved
|
|
6 IDE write concurrency enable
|
|
5 slave IDE FIFO to ISA bus preemption disable
|
|
4 IDE arbiter PCI/IDE concurrency support enable
|
|
3 PCI memory commands enable
|
|
2 PCI master IDE and IDE cycle concurrency enable
|
|
1 PCI master X-1-1-1 MIDE enable
|
|
0 reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00960 - #00963
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (IDE Controller) IDE enhanced mode:
|
|
<a name=table963></a>
|
|
Bit(s) Description (Table 00963)
|
|
7-6 secondary IDE drive 1 enhanced mode.
|
|
00 = disabled.
|
|
01 = command recovery in 1 LCLK.
|
|
10 = command recovery in 0 LCLK.
|
|
11 = reserved
|
|
5-4 secondary IDE drive 0 enhanced mode.
|
|
00 = disabled.
|
|
01 = command recovery in 1 LCLK.
|
|
10 = command recovery in 0 LCLK.
|
|
11 = reserved
|
|
3-2 primary IDE drive 1 enhanced mode.
|
|
00 = disabled.
|
|
01 = command recovery in 1 LCLK.
|
|
10 = command recovery in 0 LCLK.
|
|
11 = reserved
|
|
1-0 primary IDE drive 0 enhanced mode.
|
|
00 = disabled.
|
|
01 = command recovery in 1 LCLK.
|
|
10 = command recovery in 0 LCLK.
|
|
11 = reserved
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00960 - #00963
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi 82C750 Vendetta (IDE Controller) ultra DMA mode select:
|
|
<a name=table964></a>
|
|
Bit(s) Description (Table 00964)
|
|
15 primary IDE disable
|
|
14-12 reserved
|
|
11-10 secondary IDE drive 1 ultra DMA mode.
|
|
00 = mode 0.
|
|
01 = mode 1.
|
|
10 = mode 2.
|
|
11 = reserved
|
|
9-8 secondary IDE drive 0 ultra DMA mode (same values as bits 11-10)
|
|
7-6 primary IDE drive 1 ultra DMA mode (same values as bits 11-10)
|
|
5-4 primary IDE drive 0 ultra DMA mode (same values as bits 11-10)
|
|
3 secondary IDE drive 1 ultra DMA 33 enable
|
|
2 secondary IDE drive 0 ultra DMA 33 enable
|
|
1 primary IDE drive 1 ultra DMA 33 enable
|
|
0 primary IDE drive 0 ultra DMA 33 enable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00960
|
|
<PRE>
|
|
<p>
|
|
Format of PCI Configuration data for OPTi 82C861/82C871 PCI-to-USB Bus Bridge:
|
|
<a name=table965></a>
|
|
Offset Size Description (Table 00965)
|
|
00h 64 BYTEs header <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a>
|
|
(vendor ID 1045h, device ID C861h)
|
|
40h 4 BYTEs reserved for testing
|
|
44h 10 BYTEs reserved
|
|
4Eh BYTE I2C control
|
|
<p><b>bits 7-5:</b><br>Reserved
|
|
<p><b>bit 4:</b><br>I2C data output read-back (read-only)
|
|
<p><b>bit 3:</b><br>I2C clock output read-back (read-only)
|
|
<p><b>bit 2:</b><br>I2C data output
|
|
<p><b>bit 1:</b><br>I2C clock output
|
|
<p><b>bit 0:</b><br>I2C control enable
|
|
4Fh BYTE reserved
|
|
50h BYTE PCI host feature control
|
|
<p><b>bits 7-4:</b><br>Reserved
|
|
<p><b>bit 3:</b><br>Subsystem vendor ID register write disable
|
|
<p><b>bit 2:</b><br>CLKRUN# enable
|
|
<p><b>bit 1:</b><br>Port 2 output disable
|
|
<p><b>bit 0:</b><br>Port 1 output disable
|
|
51h BYTE interrupt assignment
|
|
<p><b>bit 7:</b><br>Host controller type
|
|
0 = Viper-N+ (send 1 data phase on IRQ driveback)
|
|
1 = FireStar (send 2 data phases on IRQ driveback)
|
|
<p><b>bit 6:</b><br>IRQ driveback enable
|
|
<p><b>bit 5:</b><br>Reserved
|
|
<p><b>bits 4-0:</b><br>Interrupt assignment
|
|
00000 = disabled
|
|
00001 = PCIRQ0# (default) to 00100 = PCIRQ3#,
|
|
00101 = ACPI0 to 01111 = ACPI10
|
|
10000 = IRQ0 to 11111 = IRQ15
|
|
52h 2 BYTEs reserved
|
|
54h DWORD IRQ driveback address
|
|
<p><b>bits 1-0:</b><br>Reserved to 00 (read-only)
|
|
58h 20 BYTEs reserved
|
|
6Ch DWORD reserved (test mode enable)
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00878 - #00929 - #00939
|
|
<PRE>
|
|
<p>
|
|
Format of OPTi FireLink/FireBlast Host Controller memory-mapped registers:
|
|
<a name=table966></a>
|
|
Offset Size Description (Table 00966)
|
|
00h 256 BYTES standard OpenHCI registers <a href="rb-2377.htm#Table902" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table902">(see #00902)</a>
|
|
100h DWORD "HceControl" emulation control <a href="rb-2383.htm#Table967" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table967">(see #00967)</a>
|
|
104h DWORD "HceInput" legacy Input Buffer <a href="rb-2383.htm#Table968" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table968">(see #00968)</a>
|
|
108h DWORD "HceOutput" legacy Output Buffer <a href="rb-2383.htm#Table969" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table969">(see #00969)</a>
|
|
10Ch DWORD "HceStatus" legacy Status <a href="rb-2383.htm#Table970" tppabs="http://www.ctyme.com/intr/rb-2383.htm#Table970">(see #00970)</a>
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00902 - #00965
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi FireLink/FireBlast "HceControl" register:
|
|
<a name=table967></a>
|
|
Bit(s) Description (Table 00967)
|
|
31-9 reserved
|
|
8 A20 gate state
|
|
7 IRQ12 active (write 1 to clear)
|
|
6 IRQ1 active (write 1 to clear)
|
|
5 A20 gate sequence.
|
|
1 D1h written to port 64h.
|
|
0 other than D1h written to port 64h
|
|
4 external IRQ emulation enable
|
|
3 IRQ enable
|
|
2 character pending emulation enable
|
|
1 (read-only) emulation interrupt condition
|
|
0 emulation enable
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00902 - PORT 0064h
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi FireLink/FireBlast "HceInput" register:
|
|
<a name=table968></a>
|
|
Bit(s) Description (Table 00968)
|
|
31-8 reserved
|
|
7-0 data written to port 60h or 64h
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00902 - #00970 - PORT 0060h - PORT 0064h
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi FireLink/FireBlast "HceOutput" register:
|
|
<a name=table969></a>
|
|
Bit(s) Description (Table 00969)
|
|
31-8 reserved
|
|
7-0 data to be returned on read of port 60h
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00902 - PORT 0060h
|
|
<PRE>
|
|
<p>
|
|
Bitfields for OPTi FireLink/FireBlast "HceStatus" register:
|
|
<a name=table970></a>
|
|
Bit(s) Description (Table 00970)
|
|
31-8 reserved
|
|
7 parity error
|
|
6 time-out
|
|
5 aux output full enable
|
|
4 keyboard inhibit switch state.
|
|
0 inhibited.
|
|
1 not inhibited
|
|
3 data written to port:.
|
|
0 port 60h.
|
|
1 port 64h
|
|
2 warm/cold boot flag
|
|
1 input full
|
|
0 output full
|
|
</PRE>
|
|
<p><b>See Also:</b>
|
|
#00902 - PORT 0060h - PORT 0064h
|
|
<p>
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