65 lines
3.1 KiB
HTML
65 lines
3.1 KiB
HTML
<html><!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN">
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<html>
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<head>
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<title>80386 Programmer's Reference Manual -- Opcode OR</title>
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</head>
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<body>
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<b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM"> NOT One's Complement Negation</a><br>
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<b>next:</b><a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM"> OUT Output to Port</a>
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<p>
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<hr>
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<p>
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<h1>OR -- Logical Inclusive OR</h1>
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<pre>
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Opcode Instruction Clocks Description
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0C ib OR AL,imm8 2 OR immediate byte to AL
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0D iw OR AX,imm16 2 OR immediate word to AX
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0D id OR EAX,imm32 2 OR immediate dword to EAX
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80 /1 ib OR r/m8,imm8 2/7 OR immediate byte to r/m byte
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81 /1 iw OR r/m16,imm16 2/7 OR immediate word to r/m word
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81 /1 id OR r/m32,imm32 2/7 OR immediate dword to r/m dword
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83 /1 ib OR r/m16,imm8 2/7 OR sign-extended immediate byte
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with r/m word
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83 /1 ib OR r/m32,imm8 2/7 OR sign-extended immediate byte
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with r/m dword
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08 /r OR r/m8,r8 2/6 OR byte register to r/m byte
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09 /r OR r/m16,r16 2/6 OR word register to r/m word
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09 /r OR r/m32,r32 2/6 OR dword register to r/m dword
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0A /r OR r8,r/m8 2/7 OR byte register to r/m byte
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0B /r OR r16,r/m16 2/7 OR word register to r/m word
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0B /r OR r32,r/m32 2/7 OR dword register to r/m dword
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</pre>
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<h2>Operation</h2>
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<pre>
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DEST := DEST OR SRC;
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CF := 0;
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OF := 0
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</pre>
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<h2>Description</h2>
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OR computes the inclusive OR of its two operands and places the result in the first operand. Each bit of the result is 0 if both corresponding bits of the operands are 0; otherwise, each bit is 1.
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<h2>Flags Affected</h2>
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OF := 0, CF := 0; SF, ZF, and PF as described in <a href="APPC.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/APPC.HTM">Appendix C</a>; AF is undefined
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<h2>Protected Mode Exceptions</h2>
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#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page fault
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<h2>Real Address Mode Exceptions</h2>
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Interrupt 13 if any part of the operand would lie outside of the effective address space from 0 to 0FFFFH
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<h2>Virtual 8086 Mode Exceptions</h2>
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Same exceptions as in real-address mode; #PF(fault-code) for a page fault
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<p>
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<hr>
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<p><b>up:</b> <a href="C17.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/C17.HTM">Chapter 17 -- 80386 Instruction Set</a><br>
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<b>prev:</b><a href="NOT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/NOT.HTM"> NOT One's Complement Negation</a><br>
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<b>next:</b><a href="OUT.HTM" tppabs="http://webster.cs.ucr.edu/Page_TechDocs/Doc386/OUT.HTM"> OUT Output to Port</a>
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</body>
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