566 lines
18 KiB
HTML
566 lines
18 KiB
HTML
<HTML>
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<HEAD>
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<!-- This HTML file has been created by texi2html 1.54
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from ../texi/make.texinfo on 19 July 2000 -->
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<TITLE>GNU make - An Introduction to Makefiles</TITLE>
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<link href="make_3.html" rel=Next>
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<link href="make_1.html" rel=Previous>
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<link href="make_toc.html" rel=ToC>
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</HEAD>
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<BODY>
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<p>Go to the <A HREF="make_1.html">first</A>, <A HREF="make_1.html">previous</A>, <A HREF="make_3.html">next</A>, <A HREF="make_19.html">last</A> section, <A HREF="make_toc.html">table of contents</A>.
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<P><HR><P>
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<H1><A NAME="SEC4" HREF="make_toc.html#TOC4">An Introduction to Makefiles</A></H1>
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<P>
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You need a file called a <STRONG>makefile</STRONG> to tell <CODE>make</CODE> what to do.
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Most often, the makefile tells <CODE>make</CODE> how to compile and link a
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program.
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<A NAME="IDX7"></A>
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</P>
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<P>
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In this chapter, we will discuss a simple makefile that describes how to
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compile and link a text editor which consists of eight C source files
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and three header files. The makefile can also tell <CODE>make</CODE> how to
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run miscellaneous commands when explicitly asked (for example, to remove
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certain files as a clean-up operation). To see a more complex example
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of a makefile, see section <A HREF="make_17.html#SEC125">Complex Makefile Example</A>.
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</P>
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<P>
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When <CODE>make</CODE> recompiles the editor, each changed C source file
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must be recompiled. If a header file has changed, each C source file
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that includes the header file must be recompiled to be safe. Each
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compilation produces an object file corresponding to the source file.
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Finally, if any source file has been recompiled, all the object files,
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whether newly made or saved from previous compilations, must be linked
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together to produce the new executable editor.
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<A NAME="IDX8"></A>
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<A NAME="IDX9"></A>
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</P>
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<H2><A NAME="SEC5" HREF="make_toc.html#TOC5">What a Rule Looks Like</A></H2>
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<P>
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<A NAME="IDX10"></A>
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<A NAME="IDX11"></A>
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<A NAME="IDX12"></A>
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</P>
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<P>
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A simple makefile consists of "rules" with the following shape:
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</P>
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<P>
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<A NAME="IDX13"></A>
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<A NAME="IDX14"></A>
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<A NAME="IDX15"></A>
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<PRE>
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<VAR>target</VAR> ... : <VAR>prerequisites</VAR> ...
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<VAR>command</VAR>
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...
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...
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</PRE>
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<P>
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A <STRONG>target</STRONG> is usually the name of a file that is generated by a
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program; examples of targets are executable or object files. A target
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can also be the name of an action to carry out, such as <SAMP>`clean'</SAMP>
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(see section <A HREF="make_4.html#SEC33">Phony Targets</A>).
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</P>
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<P>
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A <STRONG>prerequisite</STRONG> is a file that is used as input to create the
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target. A target often depends on several files.
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</P>
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<P>
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<A NAME="IDX16"></A>
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A <STRONG>command</STRONG> is an action that <CODE>make</CODE> carries out.
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A rule may have more than one command, each on its own line.
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<STRONG>Please note:</STRONG> you need to put a tab character at the beginning of
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every command line! This is an obscurity that catches the unwary.
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</P>
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<P>
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Usually a command is in a rule with prerequisites and serves to create a
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target file if any of the prerequisites change. However, the rule that
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specifies commands for the target need not have prerequisites. For
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example, the rule containing the delete command associated with the
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target <SAMP>`clean'</SAMP> does not have prerequisites.
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</P>
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<P>
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A <STRONG>rule</STRONG>, then, explains how and when to remake certain files
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which are the targets of the particular rule. <CODE>make</CODE> carries out
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the commands on the prerequisites to create or update the target. A
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rule can also explain how and when to carry out an action.
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See section <A HREF="make_4.html#SEC20">Writing Rules</A>.
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</P>
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<P>
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A makefile may contain other text besides rules, but a simple makefile
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need only contain rules. Rules may look somewhat more complicated
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than shown in this template, but all fit the pattern more or less.
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</P>
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<H2><A NAME="SEC6" HREF="make_toc.html#TOC6">A Simple Makefile</A></H2>
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<P>
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<A NAME="IDX17"></A>
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<A NAME="IDX18"></A>
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</P>
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<P>
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Here is a straightforward makefile that describes the way an
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executable file called <CODE>edit</CODE> depends on eight object files
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which, in turn, depend on eight C source and three header files.
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</P>
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<P>
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In this example, all the C files include <TT>`defs.h'</TT>, but only those
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defining editing commands include <TT>`command.h'</TT>, and only low
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level files that change the editor buffer include <TT>`buffer.h'</TT>.
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</P>
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<PRE>
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edit : main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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cc -o edit main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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main.o : main.c defs.h
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cc -c main.c
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kbd.o : kbd.c defs.h command.h
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cc -c kbd.c
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command.o : command.c defs.h command.h
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cc -c command.c
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display.o : display.c defs.h buffer.h
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cc -c display.c
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insert.o : insert.c defs.h buffer.h
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cc -c insert.c
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search.o : search.c defs.h buffer.h
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cc -c search.c
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files.o : files.c defs.h buffer.h command.h
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cc -c files.c
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utils.o : utils.c defs.h
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cc -c utils.c
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clean :
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rm edit main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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</PRE>
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<P>
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We split each long line into two lines using backslash-newline; this is
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like using one long line, but is easier to read.
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<A NAME="IDX19"></A>
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<A NAME="IDX20"></A>
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<A NAME="IDX21"></A>
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<A NAME="IDX22"></A>
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<A NAME="IDX23"></A>
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</P>
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<P>
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To use this makefile to create the executable file called <TT>`edit'</TT>,
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type:
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</P>
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<PRE>
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make
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</PRE>
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<P>
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To use this makefile to delete the executable file and all the object
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files from the directory, type:
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</P>
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<PRE>
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make clean
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</PRE>
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<P>
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In the example makefile, the targets include the executable file
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<SAMP>`edit'</SAMP>, and the object files <SAMP>`main.o'</SAMP> and <SAMP>`kbd.o'</SAMP>. The
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prerequisites are files such as <SAMP>`main.c'</SAMP> and <SAMP>`defs.h'</SAMP>.
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In fact, each <SAMP>`.o'</SAMP> file is both a target and a prerequisite.
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Commands include <SAMP>`cc -c main.c'</SAMP> and <SAMP>`cc -c kbd.c'</SAMP>.
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</P>
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<P>
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When a target is a file, it needs to be recompiled or relinked if any
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of its prerequisites change. In addition, any prerequisites that are
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themselves automatically generated should be updated first. In this
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example, <TT>`edit'</TT> depends on each of the eight object files; the
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object file <TT>`main.o'</TT> depends on the source file <TT>`main.c'</TT> and
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on the header file <TT>`defs.h'</TT>.
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</P>
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<P>
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A shell command follows each line that contains a target and
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prerequisites. These shell commands say how to update the target file.
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A tab character must come at the beginning of every command line to
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distinguish commands lines from other lines in the makefile. (Bear in
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mind that <CODE>make</CODE> does not know anything about how the commands
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work. It is up to you to supply commands that will update the target
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file properly. All <CODE>make</CODE> does is execute the commands in the rule
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you have specified when the target file needs to be updated.)
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<A NAME="IDX24"></A>
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</P>
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<P>
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The target <SAMP>`clean'</SAMP> is not a file, but merely the name of an
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action. Since you
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normally
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do not want to carry out the actions in this rule, <SAMP>`clean'</SAMP> is not a prerequisite of any other rule.
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Consequently, <CODE>make</CODE> never does anything with it unless you tell
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it specifically. Note that this rule not only is not a prerequisite, it
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also does not have any prerequisites, so the only purpose of the rule
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is to run the specified commands. Targets that do not refer to files
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but are just actions are called <STRONG>phony targets</STRONG>. See section <A HREF="make_4.html#SEC33">Phony Targets</A>, for information about this kind of target. See section <A HREF="make_5.html#SEC48">Errors in Commands</A>, to see how to cause <CODE>make</CODE> to ignore errors
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from <CODE>rm</CODE> or any other command.
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<A NAME="IDX25"></A>
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<A NAME="IDX26"></A>
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</P>
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<H2><A NAME="SEC7" HREF="make_toc.html#TOC7">How <CODE>make</CODE> Processes a Makefile</A></H2>
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<P>
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<A NAME="IDX27"></A>
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<A NAME="IDX28"></A>
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</P>
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<P>
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By default, <CODE>make</CODE> starts with the first target (not targets whose
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names start with <SAMP>`.'</SAMP>). This is called the <STRONG>default goal</STRONG>.
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(<STRONG>Goals</STRONG> are the targets that <CODE>make</CODE> strives ultimately to
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update. See section <A HREF="make_9.html#SEC87">Arguments to Specify the Goals</A>.)
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<A NAME="IDX29"></A>
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<A NAME="IDX30"></A>
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<A NAME="IDX31"></A>
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</P>
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<P>
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In the simple example of the previous section, the default goal is to
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update the executable program <TT>`edit'</TT>; therefore, we put that rule
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first.
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</P>
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<P>
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Thus, when you give the command:
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</P>
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<PRE>
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make
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</PRE>
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<P>
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<CODE>make</CODE> reads the makefile in the current directory and begins by
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processing the first rule. In the example, this rule is for relinking
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<TT>`edit'</TT>; but before <CODE>make</CODE> can fully process this rule, it
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must process the rules for the files that <TT>`edit'</TT> depends on,
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which in this case are the object files. Each of these files is
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processed according to its own rule. These rules say to update each
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<SAMP>`.o'</SAMP> file by compiling its source file. The recompilation must
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be done if the source file, or any of the header files named as
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prerequisites, is more recent than the object file, or if the object
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file does not exist.
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</P>
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<P>
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The other rules are processed because their targets appear as
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prerequisites of the goal. If some other rule is not depended on by the
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goal (or anything it depends on, etc.), that rule is not processed,
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unless you tell <CODE>make</CODE> to do so (with a command such as
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<CODE>make clean</CODE>).
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</P>
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<P>
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Before recompiling an object file, <CODE>make</CODE> considers updating its
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prerequisites, the source file and header files. This makefile does not
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specify anything to be done for them--the <SAMP>`.c'</SAMP> and <SAMP>`.h'</SAMP> files
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are not the targets of any rules--so <CODE>make</CODE> does nothing for these
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files. But <CODE>make</CODE> would update automatically generated C programs,
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such as those made by Bison or Yacc, by their own rules at this time.
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</P>
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<P>
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After recompiling whichever object files need it, <CODE>make</CODE> decides
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whether to relink <TT>`edit'</TT>. This must be done if the file
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<TT>`edit'</TT> does not exist, or if any of the object files are newer than
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it. If an object file was just recompiled, it is now newer than
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<TT>`edit'</TT>, so <TT>`edit'</TT> is relinked.
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<A NAME="IDX32"></A>
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</P>
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<P>
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Thus, if we change the file <TT>`insert.c'</TT> and run <CODE>make</CODE>,
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<CODE>make</CODE> will compile that file to update <TT>`insert.o'</TT>, and then
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link <TT>`edit'</TT>. If we change the file <TT>`command.h'</TT> and run
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<CODE>make</CODE>, <CODE>make</CODE> will recompile the object files <TT>`kbd.o'</TT>,
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<TT>`command.o'</TT> and <TT>`files.o'</TT> and then link the file <TT>`edit'</TT>.
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</P>
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<H2><A NAME="SEC8" HREF="make_toc.html#TOC8">Variables Make Makefiles Simpler</A></H2>
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<P>
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<A NAME="IDX33"></A>
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<A NAME="IDX34"></A>
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</P>
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<P>
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In our example, we had to list all the object files twice in the rule for
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<TT>`edit'</TT> (repeated here):
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</P>
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<PRE>
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edit : main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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cc -o edit main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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</PRE>
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<P>
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<A NAME="IDX35"></A>
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Such duplication is error-prone; if a new object file is added to the
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system, we might add it to one list and forget the other. We can eliminate
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the risk and simplify the makefile by using a variable. <STRONG>Variables</STRONG>
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allow a text string to be defined once and substituted in multiple places
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later (see section <A HREF="make_6.html#SEC57">How to Use Variables</A>).
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</P>
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<P>
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<A NAME="IDX36"></A>
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<A NAME="IDX37"></A>
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<A NAME="IDX38"></A>
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<A NAME="IDX39"></A>
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<A NAME="IDX40"></A>
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It is standard practice for every makefile to have a variable named
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<CODE>objects</CODE>, <CODE>OBJECTS</CODE>, <CODE>objs</CODE>, <CODE>OBJS</CODE>, <CODE>obj</CODE>,
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or <CODE>OBJ</CODE> which is a list of all object file names. We would
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define such a variable <CODE>objects</CODE> with a line like this in the
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makefile:
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</P>
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<PRE>
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objects = main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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</PRE>
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<P>
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Then, each place we want to put a list of the object file names, we can
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substitute the variable's value by writing <SAMP>`$(objects)'</SAMP>
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(see section <A HREF="make_6.html#SEC57">How to Use Variables</A>).
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</P>
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<P>
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Here is how the complete simple makefile looks when you use a variable
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for the object files:
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</P>
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<PRE>
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objects = main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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edit : $(objects)
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cc -o edit $(objects)
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main.o : main.c defs.h
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cc -c main.c
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kbd.o : kbd.c defs.h command.h
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cc -c kbd.c
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command.o : command.c defs.h command.h
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cc -c command.c
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display.o : display.c defs.h buffer.h
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cc -c display.c
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insert.o : insert.c defs.h buffer.h
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cc -c insert.c
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search.o : search.c defs.h buffer.h
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cc -c search.c
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files.o : files.c defs.h buffer.h command.h
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cc -c files.c
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utils.o : utils.c defs.h
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cc -c utils.c
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clean :
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rm edit $(objects)
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</PRE>
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<H2><A NAME="SEC9" HREF="make_toc.html#TOC9">Letting <CODE>make</CODE> Deduce the Commands</A></H2>
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<P>
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<A NAME="IDX41"></A>
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<A NAME="IDX42"></A>
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<A NAME="IDX43"></A>
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</P>
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<P>
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It is not necessary to spell out the commands for compiling the individual
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C source files, because <CODE>make</CODE> can figure them out: it has an
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<STRONG>implicit rule</STRONG> for updating a <SAMP>`.o'</SAMP> file from a correspondingly
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named <SAMP>`.c'</SAMP> file using a <SAMP>`cc -c'</SAMP> command. For example, it will
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use the command <SAMP>`cc -c main.c -o main.o'</SAMP> to compile <TT>`main.c'</TT> into
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<TT>`main.o'</TT>. We can therefore omit the commands from the rules for the
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object files. See section <A HREF="make_10.html#SEC93">Using Implicit Rules</A>.
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</P>
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<P>
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When a <SAMP>`.c'</SAMP> file is used automatically in this way, it is also
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automatically added to the list of prerequisites. We can therefore omit
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the <SAMP>`.c'</SAMP> files from the prerequisites, provided we omit the commands.
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</P>
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<P>
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Here is the entire example, with both of these changes, and a variable
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<CODE>objects</CODE> as suggested above:
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</P>
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<PRE>
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objects = main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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edit : $(objects)
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cc -o edit $(objects)
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main.o : defs.h
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kbd.o : defs.h command.h
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command.o : defs.h command.h
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display.o : defs.h buffer.h
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insert.o : defs.h buffer.h
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search.o : defs.h buffer.h
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files.o : defs.h buffer.h command.h
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utils.o : defs.h
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.PHONY : clean
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clean :
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-rm edit $(objects)
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</PRE>
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<P>
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This is how we would write the makefile in actual practice. (The
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complications associated with <SAMP>`clean'</SAMP> are described elsewhere.
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|
See section <A HREF="make_4.html#SEC33">Phony Targets</A>, and section <A HREF="make_5.html#SEC48">Errors in Commands</A>.)
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</P>
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<P>
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Because implicit rules are so convenient, they are important. You
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will see them used frequently.
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</P>
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<H2><A NAME="SEC10" HREF="make_toc.html#TOC10">Another Style of Makefile</A></H2>
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<P>
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<A NAME="IDX44"></A>
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</P>
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<P>
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When the objects of a makefile are created only by implicit rules, an
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alternative style of makefile is possible. In this style of makefile,
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you group entries by their prerequisites instead of by their targets.
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Here is what one looks like:
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</P>
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<PRE>
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objects = main.o kbd.o command.o display.o \
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insert.o search.o files.o utils.o
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edit : $(objects)
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cc -o edit $(objects)
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$(objects) : defs.h
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kbd.o command.o files.o : command.h
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display.o insert.o search.o files.o : buffer.h
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</PRE>
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<P>
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Here <TT>`defs.h'</TT> is given as a prerequisite of all the object files;
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<TT>`command.h'</TT> and <TT>`buffer.h'</TT> are prerequisites of the specific
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object files listed for them.
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</P>
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<P>
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Whether this is better is a matter of taste: it is more compact, but some
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people dislike it because they find it clearer to put all the information
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about each target in one place.
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</P>
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<H2><A NAME="SEC11" HREF="make_toc.html#TOC11">Rules for Cleaning the Directory</A></H2>
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<P>
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<A NAME="IDX45"></A>
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<A NAME="IDX46"></A>
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</P>
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<P>
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Compiling a program is not the only thing you might want to write rules
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for. Makefiles commonly tell how to do a few other things besides
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compiling a program: for example, how to delete all the object files
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and executables so that the directory is <SAMP>`clean'</SAMP>.
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</P>
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<P>
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<A NAME="IDX47"></A>
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Here is how we
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could write a <CODE>make</CODE> rule for cleaning our example editor:
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</P>
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<PRE>
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clean:
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rm edit $(objects)
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</PRE>
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<P>
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In practice, we might want to write the rule in a somewhat more
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complicated manner to handle unanticipated situations. We would do this:
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</P>
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<PRE>
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.PHONY : clean
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clean :
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-rm edit $(objects)
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</PRE>
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<P>
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This prevents <CODE>make</CODE> from getting confused by an actual file
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called <TT>`clean'</TT> and causes it to continue in spite of errors from
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<CODE>rm</CODE>. (See section <A HREF="make_4.html#SEC33">Phony Targets</A>, and section <A HREF="make_5.html#SEC48">Errors in Commands</A>.)
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</P>
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<P>
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A rule such as this should not be placed at the beginning of the
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makefile, because we do not want it to run by default! Thus, in the
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example makefile, we want the rule for <CODE>edit</CODE>, which recompiles
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the editor, to remain the default goal.
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</P>
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<P>
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Since <CODE>clean</CODE> is not a prerequisite of <CODE>edit</CODE>, this rule will not
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run at all if we give the command <SAMP>`make'</SAMP> with no arguments. In
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order to make the rule run, we have to type <SAMP>`make clean'</SAMP>.
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See section <A HREF="make_9.html#SEC85">How to Run <CODE>make</CODE></A>.
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</P>
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<P><HR><P>
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<p>Go to the <A HREF="make_1.html">first</A>, <A HREF="make_1.html">previous</A>, <A HREF="make_3.html">next</A>, <A HREF="make_19.html">last</A> section, <A HREF="make_toc.html">table of contents</A>.
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