158 lines
8.0 KiB
Plaintext
158 lines
8.0 KiB
Plaintext
Port Description
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ßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß
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000H-01fH DMA (Direct Memory Access) controller See DMA Ports
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020H-03fH Interrupt Controller
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==============================================================================
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DMA (Direct Memory Access) is used for high-speed data transfers between I/O
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devices and memory without intervention of the CPU. It is typically employed
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by diskette and hard disk drivers, but it could be used for streaming tape or
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any other device as long as it does not interfere with the operation of other
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standard devices.
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The original PC supports four 8-bit DMA channels, across a 20-bit address
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space, using an Intel 8237A DMA controller chip. The ÝATÞ supports 7 DMA
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channels by cascading a second 8237A DMA controller. The differences between
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PC and AT DMA are covered at the end of this section.
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Channel Usage in PC and XT
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ßßßßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß
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0 memory refresh (highest priority)
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1 not used
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2 diskette adapter
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3 hard disk adapter (lowest priority)
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Port Description
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ßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß
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000H-007H DMA base address an offset registers
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All are 16-bit registers: read/write the low byte, then the high byte
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at the same I/O port. Base addresses are offsets from a DMA Page (see
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below).
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000H Write: DMA channel 0 base address (also sets current address)
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Read: DMA channel 0 current address
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001H Write: DMA channel 0 base address and word count
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Read: DMA channel 0 current word count
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002H Write: DMA channel 1 base address
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Read: DMA channel 1 current address
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003H Write: DMA channel 1 base address and word count
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Read: DMA channel 1 current word count
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004H Write: DMA channel 2 base address (diskette adapter)
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Read: DMA channel 2 current address "
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005H Write: DMA channel 2 base address and word count "
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Read: DMA channel 2 current word count "
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006H Write: DMA channel 3 base address (hard disk adapter)
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Read: DMA channel 3 current address "
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007H Write: DMA channel 3 base address and word count "
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Read: DMA channel 3 current word count "
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þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ
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008H-00fH DMA control/status registers
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008H Write: DMA command register
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º ³ ³ ³ ³ ³ ³ ³ º
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ÓÒÁÒÁÒÁÒÁÒÁÒÁÒÁÒ½ bit
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º º º º º º º ÈÍ 0: 1=enable memory-to-memory DMA (ch0Ích1)
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º º º º º º ÈÍÍÍ 1: 1=enable Ch0 address hold
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º º º º º ÈÍÍÍÍÍ 2: 1=disable controller
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º º º º ÈÍÍÍÍÍÍÍ 3: 1=select compressed timing mode
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º º º ÈÍÍÍÍÍÍÍÍÍ 4: 1=enable rotating priority
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º º ÈÍÍÍÍÍÍÍÍÍÍÍ 5: 1=select extended write mode; 0=late write
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º ÈÍÍÍÍÍÍÍÍÍÍÍÍÍ 6: 1=select DRQ sensing as active high; 0=low
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ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 7: 1=select DACK sensing as active high; 0=low
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Read: DMA status register
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º ³ ³ ³ ³ ³ ³ ³ º
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ÓÄÁÄÁÄÁÄÁÄÁÄÁÄÁĽ bit
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ÈÍÍËÍͼ ÈÍÍÍÍÍÊÍ 0-3: channel 0-3 has reached terminal count
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ÈÍÍÍÍÍÍÍÍÍÍÍÍ 4-7: channel 0-3 has a request pending
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009H Write: request register
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º unused ³ ³ º
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ÓÄÁÄÁÄÁÄÁÄÁÒÁÄÁĽ bit
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º ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3)
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ÈÍÍÍÍÍ 2: 1=set request bit for channel; 0=reset request
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00aH Write: single mask bit register
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º unused ³ ³ º
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ÓÄÁÄÁÄÁÄÁÄÁÒÁÄÁĽ bit
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º ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3)
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ÈÍÍÍÍÍ 2: 1=set mask for channel; 0=clear mask (enable)
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00bH Write: mode register
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º ³ ³ ³ ³ ³ ³ ³ º
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ÓÄÁÄÁÒÁÒÁÄÁÄÁÄÁĽ bit
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È˼ º º È˼ ÈÍÊÍ 0-1: select channel (00=0; 01=1; 10=2; 11=3)
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º º º ÈÍÍÍÍÍÍ 2-3: transfer type (00=verify=Nop; 01=write; 10=read)
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º º ÈÍÍÍÍÍÍÍÍÍ 4: 1=enable auto-initialization
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º ÈÍÍÍÍÍÍÍÍÍÍÍ 5: 1=select address increment; 0=address decrement
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ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍ 6-7: 00=demand mode; 01=single; 10=block; 11=cascade
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00cH Write: clear byte pointer flip-flop. Any write clears the flip-flop so
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that the next write to any of the 16-bit registers is decoded as
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the low byte. The next is the high byte, then next is low, etc.
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00dH Write: master clear. Any OUT clears the ctrlr (must be re-initialized)
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Read: temporary reg. Last byte in memory-to-memory xfer (not used)
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00eH Write: Clear mask registers. Any OUT enables all 4 channels.
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00fH Write: master clear. Clear or mask any or all of the channels.
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Ö7Â6Â5Â4Â3Â2Â1Â0·
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º ³ ³ ³ ³ º
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ÓÄÁÄÁÄÁÄÁÒÁÒÁÒÁÒ½ bit
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º º º ÈÍ 0: 1=mask channel 0; 0=enable
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º º ÈÍÍÍ 1: 1=mask channel 1;
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º ÈÍÍÍÍÍ 2: 1=mask channel 2;
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ÈÍÍÍÍÍÍÍ 3: 1=mask channel 3;
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Read: temporary reg. Last byte in memory-to-memory xfer (not used)
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þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ
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081H-08fH DMA page registers.
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To select a starting address for a DMA operation, do an OUT to the page
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register (ports 81H-83H) for the selected channel then set the base
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address (ports 00H-07H) for the channel. A page register is set with a
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4-bit value that represents bits 16-19 of the 20-bit DMA address. Since
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the current address is a 16-bit value, it is not possible to cross a 64K
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boundary (eg, address 1000:0, 2000:0, etc.) with a DMA operation.
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081H Channel 2 page register (diskette DMA)
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082H Channel 3 page register (hard disk DMA)
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083H Channel 1 page register
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ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß
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ÚÄÄÄÄÄÄÄÄÄ¿
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³ÝATÞ DMA ³ The DMA system on the AT is basically upwardly-compatible with PC
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ÀÄÄÄÄÄÄÄÄÄÙ and XT DMA. In addition to the four 8-bit channels of the PC, the
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AT adds a second 8237A-5 DMA controller which supports channels 4-7.
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Channel Usage in AT
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ßßßßßßß ßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßßß
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0 spare Ä¿
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1 SDLC (Synchronous Data Link Control) ÆÍ 8-bit DMA channels
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2 diskette adapter ³ ³
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3 hard disk adapter ÄÙ ³
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4 (controller 2) cascade for controller 1 Ä¿ ³
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5 spare ÆÍ 16-bit DMA channels ³
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6 spare ³ ³
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7 spare ÄÙ ³
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³
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þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ³
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081H-08fH DMA page registers. On the AT, all 8 bits of the Page registers are³
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used. They become the high 8-bits of a 24-bit address space (with the ³
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low 16-bits being set in a channel's base/current address register). ³
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The page size is 128K (64K words) so DMA transfers must not cross a 128K³
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boundary (eg, address 2000:0, 4000:0, 6000:0, etc.) ³
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³
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081H Channel 2 page register (diskette DMA) (address bits 16-23) ³
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082H Channel 3 page register (hard disk DMA) (address bits 16-23) ³
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083H Channel 1 page register (address bits 16-23) ³
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087H Channel 0 page register (address bits 16-23) ³
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089H Channel 6 page register (address bits 17-23) ³
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08bH Channel 5 page register (address bits 17-23) ³
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08aH Channel 7 page register (address bits 17-23) ³
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0ceH Channel 7 current word count
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þþþþ þþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþþ
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0d0H-0dfH ÝATÞ DMA control/status registers |