93 lines
15 KiB
HTML
93 lines
15 KiB
HTML
<html><head><title>OSRC: Processor Architecture </title></head>
|
||
|
||
<body BGCOLOR=#FFFFFF TEXT=#000000 LINK=#0000FF VLINK=#0000FF ALINK=#107010>
|
||
<center><font face=Verdana size=7><b>Processor Architecture</b></font></center><blockquote>IA64, MMX, 3D-Now!, KNI, copro, optimization..</blockquote><table width="100%" cellpadding=0 cellspacing=0 border=0>
|
||
<tr><td width="33%" align=left></td>
|
||
<td width='33%' align=center></td>
|
||
<td width='33%' align=right><font size=2>[<a href="...htm" tppabs="http://www.nondot.org/~sabre/os/articles/ProcessorArchitecture/..">Up</a>]</font></td></tr>
|
||
</table><hr><p><ul><DL>
|
||
<DT><font size=+1>IA-64/Itanium:</font><br>
|
||
<ul><DL>
|
||
<DT><font size=+1><a href="../../../../../developer.intel.com/design/itanium/index.htm" tppabs="http://developer.intel.com/design/itanium/index.htm">Intel's IA64 Architecture Site</a></font> - by Intel Corp.<br>
|
||
<DD>This is a clearing house of developer information about the IA64 architecture. There are many interesting documents on it, all explaining the interesting components of the architecture... this will be the future.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/IA64_1.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/IA64_1.pdf">IA-64 Architecture - A Detailed Tutorial</a></font> - by Sverre Jarp<br>
|
||
<DD>This is an excellent tutorial on the IA-64 architecture... providing must more accessable information. It is broken into 4 distinct parts: Introduction and Overview, Multimedia Programming, Floating Point Programming, and Optimization.<p>
|
||
<DT><font size=+1><a href="../../../../../www.gcc.ml.org/epic/index.htm" tppabs="http://www.gcc.ml.org/epic/">EPIC/IA64 support for GCC</a></font> - by <a href='mailto:epic@gcc.za.org'>The EPIC Mailing List</a><br>
|
||
<DD>This site will eventually hold development information for the IA64 GCC (and all other epic versions?). Right now though, it is an excellent collection of links to a variety of sites that contain hints and clues about the Merced and other IA64 Processors (including the mysterious Elbrus E2K chip). A great source for information!<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/IA64ApplicationDevelopersArchitectureGuide.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/IA64ApplicationDevelopersArchitectureGuide.pdf">IA64 Application Developer's Guide</a></font> - by <a href="../../../../../www.intel.com/index.htm" tppabs="http://www.intel.com/">Intel Corp.</a><br>
|
||
<DD>"The first part of this document provides a comprehensive description of the IA-64 architecture, which is exposed to application software. This includes information on application level resources, the application environment, detailed application instruction descriptions, formats and encodings.<p>The second portion of this document provides a refresher on the IA-64 application architecture before describing certain IA-64 architectural features and elaborates on applying these features to generate highly optimized code."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/IA-64SoftwareConventions&RuntimeArchGuide.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/IA-64SoftwareConventions&RuntimeArchGuide.pdf">IA-64 Software Conventions and Runtime Arch Guide</a></font> - by Intel Corp.<br>
|
||
<DD>"This document describes common 64-bit software conventions for the Intel IA-64 Architecture. It does not define operating system interfaces or any conventions specific to any single operating system."<p>
|
||
</DL></ul>
|
||
<DT><font size=+1>SIMD Instruction Sets:</font><br>
|
||
<ul><DL>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/AMDMMXManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/AMDMMXManual.pdf">AMD MMX Technology Manual</a></font> - by AMD Inc.<br>
|
||
<DD>"In response to the growing need to provide improved PC multimedia capabilities, the AMD-K6 tm MMXenhanced processor is the first member in the AMD family of processors to incorporate a robust multimedia technology that is fully software compatible with the MMX technology as defined by Intel. This multimedia technology enables scaleable multimedia capabilities across a broad range of PC system price/performance points."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/3DNow!TechnologyManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/3DNow!TechnologyManual.pdf">3D-Now! Technology Manual</a></font> - by AMD Inc.<br>
|
||
<DD>"3DNow!™ Technology is a significant innovation to the x86 architecture that drives today's personal computers. 3DNow! technology is a group of new instructions that opens the traditional processing bottlenecks for floating-point-intensive and multimedia applications."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/AMDExtensionsToMMXAnd3DNow.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/AMDExtensionsToMMXAnd3DNow.pdf">AMD Extensions to MMX and 3DNow!</a></font> - by <a href="../../../../../www.amd.com/index.htm" tppabs="http://www.amd.com/">AMD Inc.</a><br>
|
||
<DD>This document describes extensions to MMX and 3DNow! added by the AMD Athlon processor family. The AMD Athlon processor adds 24 new instructions to the existing 3DNow! and MMX<4D> instruction
|
||
sets and implements additional microarchitecture enhancements that enable more efficient operation of all these instructions. In addition, they simplified the programming model by removing architectural restrictions.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/altivec_pim.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/altivec_pim.pdf">AltiVec Technology Programming Interface Manual</a></font> - by <a href="../../../../../www.mot.com/PowerPC" tppabs="http://www.mot.com/PowerPC">Motorola Inc.</a><br>
|
||
<DD>This document defines a programming model for use with the AltiVec instruction set extension to the PowerPC architecture. There are three types of programming interfaces
|
||
described in this document: 1. A high-level language interface, intended for use within programming languages
|
||
such as C or C++.
|
||
2. An application binary interface (ABI) de<64>ning low-level coding conventions. 3. An assembly language interface.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/VISInstructionSetUsersManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/VISInstructionSetUsersManual.pdf">Sun VIS Instruction Set</a></font> - by Sun Microsystems<br>
|
||
<DD>The VIS instruction set extends the Sparc V9 instruction set to make it more suitable for "multimedia" operations. This allows multiple 8 bit data types to be operated on with a single instruction, for instance...<p>
|
||
</DL></ul>
|
||
<DT><font size=+1>Chip Architectures:</font><br>
|
||
<ul><DL>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/AlphaArchitectureHandbookRev4.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/AlphaArchitectureHandbookRev4.pdf">Alpha Architecture Handbook</a></font> - by Compaq<br>
|
||
<DD>"Alpha is a 64-bit load/store RISC architecture that is designed with particular emphasis on the three elements that most affect performance: clock speed, multiple instruction issue, and multiple processors.<p>The Alpha architects examined and analyzed current and theoretical RISC architecture design elements and developed high-performance alternatives for the Alpha architecture. The architects adopted only those design elements that appeared valuable for a projected 25-year design horizon. Thus, Alpha becomes the first 21st century computer architecture."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/SparcV8ArchitectureManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/SparcV8ArchitectureManual.pdf">The Sparc Architecture Manual v8</a></font> - by Sun Microsystems<br>
|
||
<DD>"SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II designs engineered at the University of California at Berkeley from 1980 through 1982. the SPARC <20>register window<6F> architecture, pioneered in UC Berkeley designs, allows for straightforward, high-performance compilers and a significant reduction in memory load/store instructions over other RISCs, particularly for large application programs."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/SparcV9ArchitectureManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/SparcV9ArchitectureManual.pdf">The Sparc Architecture Manual v9</a></font> - by Sun Microsystems<br>
|
||
<DD>"SPARC-V9 is a robust RISC architecture that will remain competitive well into the next century. The SPARC-V9 architecture delivers oh this promise by enhancing SPARC-V8 to provide explicit support for: 64-bit virtual addresses and 64-bit integer data, improved system performance, advanced optimizing compilers, superscalar implementations, advanced operating systems, fault tolerance, extremely fast trap handling and context switching, big and little endian byte orders."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/MIPSProArchitectureVol2.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/MIPSProArchitectureVol2.pdf">MIPSpro(tm) Assembly Language Programmer's Guide</a></font> - by Silicon Graphics, Inc.<br>
|
||
<DD>"This book describes the assembly language supported by the RISCompiler system, its syntax rules, and how to write assembly programs. For information on assembling and linking an assembly language program, see the MIPSpro Compiling, Debugging and Performance Tuning Guide."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/SVR4-ABI-PPC.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/SVR4-ABI-PPC.pdf">SVR4 ABI for the Power PC</a></font><br>
|
||
<DD>This document describes the PowerPC Application Binary Interface for SVR4 Unix. It details parameter passing conventions, the OS interface, object file format, debugging format... etc. Unfortunately, it seems that the pages are in a backwards order... so the first page is page 150, the 150th page is page 1... agravating. If anyone figures out how to fix this, please let me know... :) <p>
|
||
</DL></ul>
|
||
<DT><font size=+1>Optimization:</font><br>
|
||
<ul><DL>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/PentiumOptimization.html" tppabs="http://www.nondot.org/sabre/os/files/Processors/PentiumOptimization.html">How to optimize for the Pentium family of microprocessors</a></font> - by <a href='mailto:agner@agner.org'>Agner Fog</a><br>
|
||
<DD>This is an AWESOME document that describes everything you could ever want to know about the Pentium/PMMX/PPro/PII/PIII family of chips. Everything from the microarchitecture and timing details to bugs and gotchas... this is an excellent manual.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/IntelArchitectureOptimizationManual.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/IntelArchitectureOptimizationManual.pdf">Intel Architecture Optimization Manual</a></font> - by Intel Corp.<br>
|
||
<DD>"Applications developed for the 8086/8088, 80286, Intel386 (DX or SX), and Intel486 processors will execute on the Pentium ® , Pentium Pro and Pentium II processors without any modification or recompilation. However, the following code optimization techniques and architectural information will help you tune your application to its greatest potential."<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/AMDx86CodeOptimization.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/AMDx86CodeOptimization.pdf">x86 Code Optimization for AMD Processors</a></font> - by AMD Inc.<br>
|
||
<DD>"This document contains information to assist programmers in creating optimized code for the AMD-K6 processor. This document is targeted at compiler/assembler designers and assembly language programmers writing high-performance code sequences."<p>
|
||
</DL></ul>
|
||
<DT><font size=+1>Other Information:</font><br>
|
||
<ul><DL>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/100MhzBus.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/100MhzBus.pdf">AMD 100mhz Super-7 Bus Specs</a></font> - by AMD Inc<br>
|
||
<DD>Specification for the Super-7 Series of bus interface processors. Super-7 is an extension of the normal Socket 7 boards to accomadate the 100mhz bus demanded by today's applications.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/IntelMultiProcessorSpecv1.4.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/IntelMultiProcessorSpecv1.4.pdf">Intel Multi-Processor Specification v1.4</a></font> - by Intel Corp<br>
|
||
<DD>The MultiProcessor Specification defines an enhancement to the standard to which PC manufacturers design DOS-compatible systems. MP-capable operating systems will be able to run without special customization on multiprocessor systems that comply with this specification. End users who purchase a compliant multiprocessor system will be able to run their choice of operating systems.<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/WECSSKAFloatingPoint.pdf" tppabs="http://www.nondot.org/sabre/os/files/Processors/WECSSKAFloatingPoint.pdf">What every Computer Scientist should know about Floating Point</a></font> - by David Goldberg<br>
|
||
<DD>Just like it says, this document covers just about everything about floating point. Theory, proofs, limits, and discussion are all presented for your consumption... a must have!<p>
|
||
<DT><font size=+1><a href="../../../../sabre/os/files/Processors/COPRO.ASM" tppabs="http://www.nondot.org/sabre/os/files/Processors/COPRO.ASM">FPU Detection Code</a></font><br>
|
||
<DD>This code detects the presence and the type of floating point unit (FPU) available on the current machine. It distinguishes between the 8087, 80287, 80387, and a few uncommon FPUs...<p>
|
||
</DL></ul>
|
||
</DL></ul>
|
||
<hr>
|
||
<TABLE ALIGN=RIGHT BORDER=0><TR><TD><center>
|
||
Copyright © 1995-2002 <i><a href='mailto:sabre@nondot.org'>Chris Lattner</a></i><br>
|
||
This page last modified:11/04/03<br><a href="...htm" tppabs="http://www.nondot.org/~sabre/os/articles/ProcessorArchitecture/..">Go up a level</a><br>
|
||
</center></TD></TR></TABLE>
|
||
|
||
<font size=-1>
|
||
[about] [faq]
|
||
[<a href="../../Updates/index.htm" tppabs="http://www.nondot.org/~sabre/os/Updates/">updates</a>]
|
||
[<a href="../../Stats/index.htm" tppabs="http://www.nondot.org/~sabre/os/Stats/">stats</a>]
|
||
[<a href="../../AuthorRecognition.html" tppabs="http://www.nondot.org/~sabre/os/AuthorRecognition.html">author recognition</a>]
|
||
[<a href="../../submit/index.htm" tppabs="http://www.nondot.org/~sabre/os/submit/">contributing</a>]
|
||
[<a href="../PendingQueue/index.htm" tppabs="http://www.nondot.org/~sabre/os/articles/PendingQueue/">pending submissions</a>]
|
||
[feedback]
|
||
[<a href='mailto:sabre@nondot.org'>email</a>]
|
||
[<a href="../index.htm" tppabs="http://www.nondot.org/~sabre/os/articles/">up</a>]
|
||
</font><p>
|
||
<font size=-1>
|
||
<font color=#FF0000>(new!)</font> sections have been updated in the last week...
|
||
<font color=#808000>(recent)</font> sections have been updated in the last two weeks...<br>
|
||
</font> |