117 lines
3.8 KiB
Plaintext
117 lines
3.8 KiB
Plaintext
The ATI driver is "experimental" at this stage. The information in
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this file has been taken from comments in x386/vga256/drivers/ati/driver.c
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Also refer to the program ati.test.c in /usr/X386/lib/X11/etc.
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For further details, contact Rik Faith <faith@cs.unc.edu>.
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* This is the X11R5 x386 driver for ATI VGA WONDER video adapters. At
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* present, this drive works best with ATI VGA WONDER PLUS and ATI VGA
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* WONDER XL cards with the ATI18810 dot clock and the ATI28800-5 chip.
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* ATI VGA WONDER cards with other chips revisions may not function as
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* desired.
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* I've come to believe the people who design these cards couldn't
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* allow for future enhancements if their life depended on it!
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* The register set architecture is a joke!
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* NOTES:
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*
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* 1) The ATI 18800/28800 use a special registers for their extended
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* features. There is one index and one data register. Under MS-DOS this
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* should be specified by reading C000:10. But since we cannot read this
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* now, let's use the same fixed address as our unix kernel does:
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* 0x1CE/0x1CF. I also got these ports form a second source, thus it seems
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* to be safe to use them.
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*
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* This comment is no longer valid. We read C000:10.
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*
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* 2) The ATI 18800/28800 extended registers differ in their i/o behaviour
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* from the normal ones:
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*
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* write: outw(0x1CE, (data << 8) | index);
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* read: outb(0x1CE, index); data = inb(0x1CF);
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*
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* Two consecutive byte-writes are NOT allowed. Furthermore is a index
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* written to 0x1CE only usable ONCE !!!
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*
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* More notes by dje ...
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*
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* 3) I've tried to allow for a future when this code drives all VGA Wonder
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* cards. To do this I had decide what to do with the clock values. Boards
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* prior to V5 use 4 crystals. Boards V5 and later use a clock generator
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* chip. Just to complicate things a bit, V3 and V4 boards aren't
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* compatible when it comes to choosing clock frequencies. :-(
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*
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* V3/V4 Board Clock Frequencies
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* R E G I S T E R S
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* 1CE(*) 3C2 3C2 Frequency
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* B2h/BEh
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* Bit 6/4 Bit 3 Bit 2
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* --------- ------- ------- ---------
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* 0 0 0 50.175
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* 0 0 1 56.644
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* 0 1 0 Spare 1
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* 0 1 1 44.900
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* 1 0 0 44.900
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* 1 0 1 50.175
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* 1 1 0 Spare 2
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* 1 1 1 36.000
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*
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* (*): V3 uses Index B2h, bit 6; V4 uses Index BEh, bit 4.
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*
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* V5,Plus,XL Board Clock Frequencies
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* R E G I S T E R S
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* 1CE 1CE 3C2 3C2 Frequency
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* BEh B9h
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* Bit 4 Bit 1 Bit 3 Bit 2
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* ------- ------- ------- ------- ---------
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* 1 0 0 0 42.954
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* 1 0 0 1 48.771
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* 1 0 1 0 External 0 (16.657)
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* 1 0 1 1 36.000
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* 1 1 0 0 50.350
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* 1 1 0 1 56.640
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* 1 1 1 0 External 1 (28.322)
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* 1 1 1 1 44.900
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* 0 0 0 0 30.240
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* 0 0 0 1 32.000
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* 0 0 1 0 37.500
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* 0 0 1 1 39.000
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* 0 1 0 0 40.000
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* 0 1 0 1 56.644
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* 0 1 1 0 75.000
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* 0 1 1 1 65.000
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*
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* For all of the above (V3,V4,V5,Plus,XL), these frequencies can be
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* divided by 1, 2, 3, or 4:
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*
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* Reg 1CE, Index B8h
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* Bit 7 Bit 6
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* 0 0 Divide by 1
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* 0 1 Divide by 2
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* 1 0 Divide by 3
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* 1 1 Divide by 4
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*
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* What I've done is the following. The clock values specified in Xconfig
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* shall be:
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*
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* 18 22 25 28 36 44 50 56
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* 30 32 37 39 40 0 75 65 (duplicate 56: --> 0)
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*
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* The first row is usable on all VGA Wonder cards. The second row is
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* only usable on V5,Plus,XL cards. The code in ATIInit() will map these
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* clock values into the appropriate bit settings for each of the cards.
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* Some of these clock choices aren't really usable, think of these as
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* place holders.
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*
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* 4) The ATI Programmer's Reference Manual lacked enough prose to explain
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* what the various bits of all of the various registers do. It is
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* entirely reasonable to believe some of the choices I've made are
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* imperfect because I didn't understand what I was doing.
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*
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* 5) V3 board support needs a lot of work. I suspect it isn't worth it.
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