219 lines
13 KiB
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219 lines
13 KiB
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<TITLE>Int 1A/AX=B10Ah/SF=100Bh
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Int 1A/AX=B10Ah/SF=100Bh - PCI BIOS v2.0c+ - READ CONFIGURATION DWORD (National Semicond. device) -
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AX = B10Ah subfn 100Bh
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh) (see #00878)
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Return: CF clear if successful
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ECX = dword read
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CF set on error
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AH = status (00h,87h) (see #00729)
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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<h2>Int 1A/AX=B10Ah/SF=100Bh
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<h3><font color=#C00040>PCI BIOS v2.0c+ - READ CONFIGURATION DWORD (National Semicond. device)</font></h3>
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<PRE>
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AX = B10Ah subfn 100Bh
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh) <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a><br>
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<p><b>Return:</b><br>CF clear if successful
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ECX = dword read
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CF set on error
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AH = status (00h,87h) <a href="rb-2371.htm#Table729" tppabs="http://www.ctyme.com/intr/rb-2371.htm#Table729">(see #00729)</a>
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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</PRE>
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<p><b>Notes:</b>
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This function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call.
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The meanings of BL and BH on entry were exchanged between the initial
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drafts of the specification and final implementation
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<p><b>See Also:</b>
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<a href="rb-2377.htm" tppabs="http://www.ctyme.com/intr/rb-2377.htm">AX=B10Ah</a> - <a href="rb-2387.htm" tppabs="http://www.ctyme.com/intr/rb-2387.htm">AX=B10Ah/SF=8086h</a>
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<PRE>
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<p>
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Format of National Semiconductor PC87410 EIDE Controller configuration:
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<a name=table921></a>
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Offset Size Description (Table 00921)
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00h 64 BYTEs header <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a>
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(vendor ID 100Bh, device ID D001h)
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<p><b>10h DWORD I/O base address for channel 0 control ports (def:</b><br>01F0h)
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<p><b>14h DWORD I/O base address for channel 0 status port (def:</b><br>03F6h)
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<p><b>18h DWORD I/O base address for channel 1 control ports (def:</b><br>0170h)
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<p><b>1Ch DWORD I/O base address for channel 1 status port (def:</b><br>0376h)
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40h BYTE IDE Channel 0 timing control
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41h WORD IDE Channel 0 read-ahead counter (write-only except bit 15)
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43h BYTE IDE Channel 0 function
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44h BYTE IDE Channel 1 timing control
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45h WORD IDE Channel 1 read-ahead counter (write-only except bit 15)
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47h BYTE IDE Channel 1 function
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48h BYTE PCI control
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49h 7 BYTEs unused
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50h 176 BYTEs ??? (unused?)
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!!!http://www.national.com/ds/PC/PC87410.pdf p.7
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</PRE>
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<p><b>See Also:</b>
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#00739 - #00922
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<PRE>
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<p>
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Format of National Semiconductor PC87415 IDE DMA-Master configuration:
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<a name=table922></a>
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Offset Size Description (Table 00922)
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00h 64 BYTEs header <a href="rb-2377.htm#Table878" tppabs="http://www.ctyme.com/intr/rb-2377.htm#Table878">(see #00878)</a>
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(vendor ID 100Bh, device ID 0002h)
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40h 3 BYTEs control register
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43h BYTE write buffer status (read-only)
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44h BYTE Channel 1 master read timing
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45h BYTE Channel 1 master write timing
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48h BYTE Channel 1 slave read timing
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49h BYTE Channel 1 slave write timing
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4Ch BYTE Channel 2 master read timing
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4Dh BYTE Channel 2 master write timing
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50h BYTE Channel 2 slave read timing
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51h BYTE Channel 2 slave write timing
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54h BYTE command and control block timing
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55h BYTE sector size
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!!!http://www.national.com/ds/PC/PC87415.pdf p.8
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</PRE>
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<p><b>See Also:</b>
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#00739 - #00921
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<p>
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<b>Category: <a href="cat-014.htm" tppabs="http://www.ctyme.com/intr/cat-014.htm">
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Expansion Bus Bios</a>
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- <a href="int-1a-1.htm" tppabs="http://www.ctyme.com/intr/int-1A.htm">
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Int 1Ah</a>
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